On 20.03.2024 12:45, Andrew Cooper wrote: > On 20/03/2024 8:12 am, Jan Beulich wrote: >> On 19.03.2024 18:40, Andrew Cooper wrote: >>> It occurs to me that I need this hunk too. >>> >>> diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py >>> index 25d329ce486f..bf3f9ec01e6e 100755 >>> --- a/xen/tools/gen-cpuid.py >>> +++ b/xen/tools/gen-cpuid.py >>> @@ -329,6 +329,10 @@ def crunch_numbers(state): >>> # In principle the TSXLDTRK insns could also be considered >>> independent. >>> RTM: [TSXLDTRK], >>> >>> + # Enhanced Predictive Store-Forwarding is a informational note >>> on top >>> + # of PSF. >>> + PSFD: [EPSF], >>> + >>> # The ARCH_CAPS CPUID bit enumerates the availability of the >>> whole register. >>> ARCH_CAPS: list(range(RDCL_NO, RDCL_NO + 64)), >>> >>> >>> To cause EPSF to disappear properly when levelling. >> What exactly is wrong with exposing EPSF when PSFD is not there? > > https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/white-papers/security-analysis-of-amd-predictive-store-forwarding.pdf > > Final sentence before the conclusion: > > "Software can determine the presence of EPSF through CPUID Fn8000_0021 > EAX[18]. All processors that support EPSF will also support PSFD." > > i.e. you'll never see anything about PSF without having the controls to > turn it off.
Ah, I only had an old copy of that. My R-b holds then with that addition. Jan
