On Tue, Oct 6, 2009 at 9:55 AM, <ge...@plan9.bell-labs.com> wrote: > The cortex-a8 arms are arm v7-a architecture. L2 page table > entries have changed format. The a8 includes trustzone, so > many registers have forked, producing a "secure" and a "nonsecure" > version of the register. The arm v7-a manual is a 2,150-page pdf > file and the omap35x SoC manual is a 3,500-page pdf file; both > documents refer you to other documents for some details. Some > co-processor control registers that used to exist to clear caches > and TLBs have vanished. I'm sure there's more that I've blocked. > >
as bad as the ARM may be, it can't hold a candle to what the pentium has become: 1. RISC CPU (undocumented) in the northbridge (MCH) running ThreadX 2. RISC CPU in the Ethernet part running ThreadX 3. Simple CPU in the southbridge (ICH) running, well, who knows. But the entire system won't come up without that CPU coming up, and the code for that CPU is (of course!) never going to be available in any general sense. (1) and (2) hold conversations with each other. Doing what? You're not supposed to know. All of this stuff is without any useful docs -- intentionally. You can't write code for (1) and (2) because the code in the FLASH has to be signed with Intel's private key, public version of which is *burned into the chip in read-only registers*. How much do you feel like trusting this platform? Daniel Liu of RIT studied (1) and (2) this summer, we're going to drop a paper into some publication this fall we hope. PCs used to be open. They are now quite closed. I am holding out hope for the ARM as the next open thing. I realize the OMAP 35 manual is long, but at least there is a manual you can get! ron
