should add irq type and interrupt counts to a arch file like erik did in 9atom. but for now, some awk did the trick.
theres the mp table from sl's t61. (sorry for the raw nature of this dump) processor: 00 00 14 03 FB 06 00 00 FF FB EB BF 00 00 00 00 00 00 00 00 processor: 00 01 14 01 FB 06 00 00 FF FB EB BF 00 00 00 00 00 00 00 00 bus: 01 00 50 43 49 20 20 20 (PCI.0) bus: 01 03 50 43 49 20 20 20 (PCI.3) bus: 01 15 50 43 49 20 20 20 (PCI.21) bus: 01 16 49 53 41 20 20 20 (ISA.22) ioapic: 02 02 20 01 00 00 C0 FE (ioapic 2 @ FEC00000) iointr: 03 03 05 00 16 00 02 00 (Ext, ISA.22, irq0, ioapic 2 @ intin0) iointr: 03 00 05 00 16 01 02 01 (Int, ISA.22, irq1, ioapic 2 @ intin1) iointr: 03 00 05 00 16 00 02 02 (Int, ISA.22, irq0, ioapic 2 @ intin2) iointr: 03 00 05 00 16 03 02 03 (Int, ISA.22, irq3, ioapic 2 @ intin3) iointr: 03 00 05 00 16 04 02 04 (Int, ISA.22, irq4, ioapic 2 @ intin4) iointr: 03 00 05 00 16 05 02 05 (Int, ISA.22, irq5, ioapic 2 @ intin5) iointr: 03 00 05 00 16 06 02 06 ..... iointr: 03 00 05 00 16 07 02 07 iointr: 03 00 05 00 16 08 02 08 iointr: 03 00 05 00 16 09 02 09 iointr: 03 00 05 00 16 0A 02 0A iointr: 03 00 05 00 16 0B 02 0B iointr: 03 00 05 00 16 0C 02 0C iointr: 03 00 05 00 16 0D 02 0D iointr: 03 00 05 00 16 0E 02 0E iointr: 03 00 05 00 16 0F 02 0F lintr: 04 03 05 00 16 00 FF 00 lintr: 04 01 05 00 16 00 FF 01 as i said before, this mp table of this machine identity maps all irq's to isa interrupts wich are edge triggered. mpintrenablex() code refused to share edge triggered interrupts causing half the usb controllers not receiving ther irq's in mp mode. if we allow sharing these edge triggered interrupts, then usb starts working. (but it might miss interrupts from time to time) this change is commited in the repository, but havnt build a new iso yet. to get the real pci irq mapping one would need to implement acpi interpreter. :( -- cinap
