Thanks Richard, This looks like it fits the bill: open, small, simple. How was it formally verified?
This doesn’t seem to need any of the chisel/scala suff, which is great. How can I help with the compiler port? Which fpga board do you recommend? Chris On Sep 6, 2018, at 1:48 PM, Richard Miller <9f...@hamnavoe.com> wrote: >> It could be, but after having looked briefly at the size of the design for >> RISC-V Rocket and especially BOOM I wonder if it's all overly complicated. >> They even built their own high level hardware language (Chisel) that >> generates Verilog using Scala. Yuck. > > It's possible to build a simple and perfectly usable RISC-V processor > on an FPGA in verilog. The one I use is > https://github.com/cliffordwolf/picorv32 , written by Clifford Wolf. > Its small size means it can be (and has been) formally verified, and > (for some applications at least) you can compensate for the modest > performance by putting lots of them on one chip. > >> Also, there's appears to be quite alot of compiler optimizations in gcc for >> RISC-based chips. > > Again, it's possible to build a simple and perfectly usable C compiler > for RISC-V without going overboard with optimisation. I've been > working on re-targeting the Plan 9 C toolchain for RISC-V. It's at > the stage where it can successfully compile itself, but floating point > support is not yet complete. If anyone is interested, let me know. >
