https://bugzilla.kernel.org/show_bug.cgi?id=221957
Xavier M ([email protected]) changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |[email protected] --- Comment #1 from Xavier M ([email protected]) --- Created attachment 311300 --> https://bugzilla.kernel.org/attachment.cgi?id=311300&action=edit DSDT fix: add UPGP() branch for XDID 0x43D5 using PT2 (B450 = 4 SuperSpeed ports) Same bug on the sister board ASUS ROG STRIX B450-E GAMING, and still present in the newest BIOS. - BIOS 6102 (2026-08-26, AGESA ComboV2 PI 1.2.0.12) and earlier 4007 (2020-12-08): both affected. - Ryzen 9 3950X, Linux 7.0.0 (Ubuntu 26.04), ACPICA 20251212, legacy/CSM boot. - Chipset xHCI 1022:43d5 at \_SB_.PCI0.GPP2.PTXH; 63 x AE_AML_UNINITIALIZED_ELEMENT per boot on PTXH.RHUB.POTx/POxx._PLD. - DSDT has the identical code: USBP is an empty Package (0x16){}; UPGP() fills it only for XDID 0x43B9/0x43D0 (PT4), 0x43BB (PT2), 0x43BC (PT1), no branch for 0x43D5, no Else. Note on the suggested fix: PT4 is probably the wrong table for B450. The 43d5 controller's xHCI Supported Protocol capabilities report 4 SuperSpeed ports: USB 3.1 ports 1-2, USB 3.0 ports 3-4, USB 2.0 ports 5-14 PT2 = {1,2,3,4, 1,2,3,4,5,...} matches that (same 4-SS layout as B350 / 0x43BB): USB2 ports 5-8 get group positions 1-4 and pair with SS ports 1-4, which is also the peering Linux infers here. PT4 = {1..8, 1..14} is laid out for 8 SS ports (X370/X470, 0x43B9/0x43D0); on B450 it silences the errors but gives USB2 ports 5-8 positions 5-8, so they no longer pair with their SS ports. Proposed: add ElseIf ((XDID == 0x43D5)) { copy PT2 } (patch attached). -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug. _______________________________________________ acpi-bugzilla mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/acpi-bugzilla
