On Thu, 2006-09-28 at 11:23 +0200, Jan Kiszka wrote:
> Philippe Gerum wrote:
> > On Thu, 2006-09-28 at 11:15 +0200, Jan Kiszka wrote:
> >> Philippe Gerum wrote:
> >>> On Mon, 2006-09-25 at 09:35 +0200, Jan Kiszka wrote:
> >>>
> >>> This one won't work. We need to forcibly re-enable the hw IRQs upon root
> >>> unstall requests, regardless of the fact that interrupts are pending in
> >>> the log; some code rely on this. E.g. Adeos/ppc over 2.4 would remain
> >>> stuck in the delay calibration routine, but there are other more tricky
> >>> places where this would bite too.
> >> But this would be ok?
> >>
> >> #else /* !CONFIG_SMP */
> >> __clear_bit(IPIPE_STALL_FLAG,
> >> &ipipe_root_domain->cpudata[cpuid].status);
> >>
> >> if (unlikely(ipipe_root_domain->cpudata[cpuid].irq_pending_hi !=
> >> 0)) {
> >> local_irq_disable_hw();
> >> __ipipe_sync_pipeline(IPIPE_IRQMASK_ANY);
> >> }
> >> local_irq_enable_hw();
> >> #endif /* CONFIG_SMP */
> >>
> >> So we can still save one disable IRQ in the fastpath.
> >>
> >
> > But in such a case, you would have to use clear_bit() to keep atomicity.
>
> This is for UP, not SMP.
>
This is not a UP vs SMP issue, the stall bit is strictly CPU local
anyway. The issue is that some archs do _not_ have intrinsically atomic
bitops; they need to emulate them by masking interrupts around the bit
setting operation. Using __clear_bit() in this context would make this
code preemptible by an interrupt in the middle of the bitop. Disabling
hw IRQs on entry allows us to use non-atomic bitops.
> Jan
>
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--
Philippe.
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