Peter Ritchie wrote: > > It's very clear with respect to CPU caching. Monitor.Enter is an > implicit > memory barrier, all CPU cached writes will be flushed to RAM (meant > specifically for the object being locked; but most processors don't > have > that level of granularity so the whole cache is flushed).
I tended to think of memory barriers from the other direction. There is the potential for a lot of magic in the hardware, and cache is just one part of the magic. The barrier might require a flush, or a write into cache, or some processor specific memory coherency magic that modern processors are pretty good at. In the end I didn't think about caches and registers, but about publishing writes for others to see *in a specific order*. That's all we need to guarantee. --s =================================== This list is hosted by DevelopMentor® http://www.develop.com View archives and manage your subscription(s) at http://discuss.develop.com
