On Sun, Nov 27, 2005 at 01:27:52PM -0500, Ben Goertzel wrote:
> "
> There are very few interesting problems that
> fit in 256K, and the performance penalty for accessing "external" memory is
> very substantial.
> "

The same applies to today's caches. The Cell attempts to reduce
memory latency by reducing the number of gate delays required
to address a block of memory, and using freed circuitry to
implement more CPU cores and more on-die memory.

The Cell will purportedly come with a high-performance interface
to main core. 
 
> Clearly, this is a very significant point.  For most useful AI
> applications using the Cell processor, it would seem to be necessary
> to have the SPE's access external memory frequently.

A good way to utilize the Cell is to stream sequentially though memory
mostly in burst mode, and process e.g. a locally constrained connectivity
network in the on-die memory before flushing it back out the core. 

Anything resulting in random accesses memory off-die will perform 
horribly on any modern hardware (that's why some benchmarks have
only 5% of best case performance).
 
> For a GP application, the program trees being evaluated would easily
> fit in much less 256K, and the evaluator could be written so as to fit
> within the 256K also.  However, to evaluate a program tree (assuming a
> data-intensive fitness function, which is the interesting case), calls
> to data in the main memory would need to be made frequently.  If this
> is really slow then the application to GP wouldn't work effectively.

A lot depends on how inexpensive and performant the actual shipped
hardware will be. We already have simulators (you'll need Fedora Core 4
to run it) but these numbers without actual hardware are useless.
 
-- 
Eugen* Leitl <a href="http://leitl.org";>leitl</a>
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