Update of /cvsroot/alsa/alsa-kernel/pci
In directory sc8-pr-cvs1:/tmp/cvs-serv4921/pci
Modified Files:
als4000.c cs4281.c es1968.c
Log Message:
Sync with the kernel tree
Index: als4000.c
===================================================================
RCS file: /cvsroot/alsa/alsa-kernel/pci/als4000.c,v
retrieving revision 1.18
retrieving revision 1.19
diff -u -r1.18 -r1.19
--- als4000.c 4 Dec 2002 17:56:16 -0000 1.18
+++ als4000.c 25 Feb 2003 13:35:40 -0000 1.19
@@ -370,7 +370,7 @@
snd_pcm_period_elapsed(chip->playback_substream);
if ((gcr_status & 0x40) && (chip->capture_substream)) /* capturing */
snd_pcm_period_elapsed(chip->capture_substream);
- if ((gcr_status & 0x10) && (chip->rmidi)) /* MPU401 interupt */
+ if ((gcr_status & 0x10) && (chip->rmidi)) /* MPU401 interrupt */
snd_mpu401_uart_interrupt(irq, chip->rmidi, regs);
/* release the gcr */
outb(gcr_status, chip->alt_port + 0xe);
Index: cs4281.c
===================================================================
RCS file: /cvsroot/alsa/alsa-kernel/pci/cs4281.c,v
retrieving revision 1.36
retrieving revision 1.37
diff -u -r1.36 -r1.37
--- cs4281.c 31 Jan 2003 15:20:03 -0000 1.36
+++ cs4281.c 25 Feb 2003 13:35:41 -0000 1.37
@@ -87,7 +87,7 @@
#define BA0_HISR_MIDI (1<<22) /* MIDI port interrupt */
#define BA0_HISR_FIFOI (1<<20) /* FIFO polled interrupt */
#define BA0_HISR_DMAI (1<<18) /* DMA interrupt (half or end) */
-#define BA0_HISR_FIFO(c) (1<<(12+(c))) /* FIFO channel interupt */
+#define BA0_HISR_FIFO(c) (1<<(12+(c))) /* FIFO channel interrupt */
#define BA0_HISR_DMA(c) (1<<(8+(c))) /* DMA channel interrupt */
#define BA0_HISR_GPPI (1<<5) /* General Purpose Input (Primary chip) */
#define BA0_HISR_GPSI (1<<4) /* General Purpose Input (Secondary chip) */
Index: es1968.c
===================================================================
RCS file: /cvsroot/alsa/alsa-kernel/pci/es1968.c,v
retrieving revision 1.34
retrieving revision 1.35
diff -u -r1.34 -r1.35
--- es1968.c 25 Feb 2003 12:35:44 -0000 1.34
+++ es1968.c 25 Feb 2003 13:35:41 -0000 1.35
@@ -1132,7 +1132,7 @@
}
spin_lock_irqsave(&chip->reg_lock, flags);
- /* clear WP interupts */
+ /* clear WP interrupts */
outw(1, chip->io_port + 0x04);
/* enable WP ints */
outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port +
ESM_PORT_HOST_IRQ);
@@ -1263,7 +1263,7 @@
}
spin_lock_irqsave(&chip->reg_lock, flags);
- /* clear WP interupts */
+ /* clear WP interrupts */
outw(1, chip->io_port + 0x04);
/* enable WP ints */
outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port +
ESM_PORT_HOST_IRQ);
@@ -1828,7 +1828,7 @@
apu_set_register(chip, apu, 10, 0x8F08);
apu_set_register(chip, apu, 11, 0x0000);
spin_lock_irqsave(&chip->reg_lock, flags);
- outw(1, chip->io_port + 0x04); /* clear WP interupts */
+ outw(1, chip->io_port + 0x04); /* clear WP interrupts */
outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port +
ESM_PORT_HOST_IRQ); /* enable WP ints */
spin_unlock_irqrestore(&chip->reg_lock, flags);
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