Following information was obtained by trial-and-error.
Use it at your own risk!
TRAM setup:
TCBS (0x44) and TCB (0x41) has same meaning as on SB Live
Internal TRAM size is 0x4000 (16 bits words)
Max external TRAM size is 0x100000 (16 bits words) - as on SB Live
Register description:
0xdb - Internal TRAM Delay Base Address Counter - is in sync with
0xde - but only 0x3fff wide
0xde - External TRAM Delay Base Address Counter
0x100 - 0x1ff - tram access control registers (?)
- only 5 bit valid
bits : 4 - 0 - use log. compresion on write and read
1 - use raw access - data from/to tram are
read/wrote
as 16 bit samples
bits : 3210 - ???
0010 - read from tram
0110 - write to tram
others - ?????
0x200 - 0x2ff - tram access data registers
- same as on SB Live
0x300 - 0x3ff - tram access address registers
- address format - host: 32 bit offset 20 bit integer part +
12 bit fractional part
to set offset to 0x123(SB Live) - 0x123 << 11 (Audigy)
- address format - DSP: same as SB Live ???
internal TRAM has index 0x00 - 0xbf
external TRAM has index 0xc0 - 0xff
Peter Zubaj
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