From: Leo Liu <leo....@amd.com>

Signed-off-by: Leo Liu <leo....@amd.com>
Acked-by: Alex Deucher <alexander.deuc...@amd.com>
---
 tests/amdgpu/cs_tests.c | 37 +++++++++++++++++++++++--------------
 1 file changed, 23 insertions(+), 14 deletions(-)

diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c
index 82c55aa..0885d97 100644
--- a/tests/amdgpu/cs_tests.c
+++ b/tests/amdgpu/cs_tests.c
@@ -168,25 +168,25 @@ static int submit(unsigned ndw, unsigned ip)
                                         AMDGPU_TIMEOUT_INFINITE,
                                         0, &expired);
        if (r)
                return r;
 
        return 0;
 }
 
 static void uvd_cmd(uint64_t addr, unsigned cmd, int *idx)
 {
-       ib_cpu[(*idx)++] = 0x3BC4;
+       ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC4 : 0x81C4;
        ib_cpu[(*idx)++] = addr;
-       ib_cpu[(*idx)++] = 0x3BC5;
+       ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC5 : 0x81C5;
        ib_cpu[(*idx)++] = addr >> 32;
-       ib_cpu[(*idx)++] = 0x3BC3;
+       ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC3 : 0x81C3;
        ib_cpu[(*idx)++] = cmd << 1;
 }
 
 static void amdgpu_cs_uvd_create(void)
 {
        struct amdgpu_bo_alloc_request req = {0};
        amdgpu_bo_handle buf_handle;
        uint64_t va = 0;
        amdgpu_va_handle va_handle;
        void *msg;
@@ -204,24 +204,26 @@ static void amdgpu_cs_uvd_create(void)
                                  &va_handle, 0);
        CU_ASSERT_EQUAL(r, 0);
 
        r = amdgpu_bo_va_op(buf_handle, 0, 4096, va, 0, AMDGPU_VA_OP_MAP);
        CU_ASSERT_EQUAL(r, 0);
 
        r = amdgpu_bo_cpu_map(buf_handle, &msg);
        CU_ASSERT_EQUAL(r, 0);
 
        memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg));
+
        if (family_id >= AMDGPU_FAMILY_VI) {
                ((uint8_t*)msg)[0x10] = 7;
-               /* chip polaris 10/11 */
-               if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) {
+               /* chip beyond polaris 10/11 */
+               if ((family_id == AMDGPU_FAMILY_AI) ||
+                   (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) {
                        /* dpb size */
                        ((uint8_t*)msg)[0x28] = 0x00;
                        ((uint8_t*)msg)[0x29] = 0x94;
                        ((uint8_t*)msg)[0x2A] = 0x6B;
                        ((uint8_t*)msg)[0x2B] = 0x00;
                }
        }
 
        r = amdgpu_bo_cpu_unmap(buf_handle);
        CU_ASSERT_EQUAL(r, 0);
@@ -280,27 +282,29 @@ static void amdgpu_cs_uvd_decode(void)
        CU_ASSERT_EQUAL(r, 0);
 
        r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
                            AMDGPU_VA_OP_MAP);
        CU_ASSERT_EQUAL(r, 0);
 
        r = amdgpu_bo_cpu_map(buf_handle, (void **)&ptr);
        CU_ASSERT_EQUAL(r, 0);
 
        memcpy(ptr, uvd_decode_msg, sizeof(uvd_create_msg));
+
        if (family_id >= AMDGPU_FAMILY_VI) {
                ptr[0x10] = 7;
                ptr[0x98] = 0x00;
                ptr[0x99] = 0x02;
-               /* chip polaris10/11 */
-               if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) {
-                       /*dpb size */
+               /* chip beyond polaris10/11 */
+               if ((family_id == AMDGPU_FAMILY_AI) ||
+                   (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) {
+                       /* dpb size */
                        ptr[0x24] = 0x00;
                        ptr[0x25] = 0x94;
                        ptr[0x26] = 0x6B;
                        ptr[0x27] = 0x00;
                        /*ctx size */
                        ptr[0x2C] = 0x00;
                        ptr[0x2D] = 0xAF;
                        ptr[0x2E] = 0x50;
                        ptr[0x2F] = 0x00;
                }
@@ -328,39 +332,44 @@ static void amdgpu_cs_uvd_decode(void)
 
        msg_addr = va;
        fb_addr = msg_addr + 4*1024;
        if (family_id >= AMDGPU_FAMILY_VI) {
                it_addr = fb_addr + 4*1024;
                bs_addr = it_addr + 4*1024;
        } else
                bs_addr = fb_addr + 4*1024;
        dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
 
-       if ((family_id >= AMDGPU_FAMILY_VI) &&
-               (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) {
-               ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
+       if (family_id >= AMDGPU_FAMILY_VI) {
+               if ((family_id == AMDGPU_FAMILY_AI) ||
+                   (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) {
+                       ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
+               }
        }
 
        dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
 
        i = 0;
        uvd_cmd(msg_addr, 0x0, &i);
        uvd_cmd(dpb_addr, 0x1, &i);
        uvd_cmd(dt_addr, 0x2, &i);
        uvd_cmd(fb_addr, 0x3, &i);
        uvd_cmd(bs_addr, 0x100, &i);
+
        if (family_id >= AMDGPU_FAMILY_VI) {
                uvd_cmd(it_addr, 0x204, &i);
-               if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)
+               if ((family_id == AMDGPU_FAMILY_AI) ||
+                   (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A))
                        uvd_cmd(ctx_addr, 0x206, &i);
-}
-       ib_cpu[i++] = 0x3BC6;
+       }
+
+       ib_cpu[i++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC6 : 0x81C6;
        ib_cpu[i++] = 0x1;
        for (; i % 16; ++i)
                ib_cpu[i] = 0x80000000;
 
        r = submit(i, AMDGPU_HW_IP_UVD);
        CU_ASSERT_EQUAL(r, 0);
 
        /* TODO: use a real CRC32 */
        for (i = 0, sum = 0; i < dt_size; ++i)
                sum += ptr[i];
-- 
2.7.4

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