> +}; > + > +static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, > + struct amdgpu_irq_src *src, > + unsigned type, > + enum amdgpu_interrupt_state state) > +{ > + struct amdgpu_vmhub *hub; > + u32 tmp, reg, bits, i; > + > + switch (state) { > + case AMDGPU_IRQ_STATE_DISABLE: > + /* MM HUB */ > + hub = &adev->vmhub[AMDGPU_MMHUB]; > + bits = hub->get_vm_protection_bits(); > + for (i = 0; i< 16; i++) { > + reg = hub->vm_context0_cntl + i; > + tmp = RREG32(reg); > + tmp &= ~bits; > + WREG32(reg, tmp); > + } > + > + /* GFX HUB */ > + hub = &adev->vmhub[AMDGPU_GFXHUB]; > + bits = hub->get_vm_protection_bits(); > + for (i = 0; i < 16; i++) { > + reg = hub->vm_context0_cntl + i; > + tmp = RREG32(reg); > + tmp &= ~bits; > + WREG32(reg, tmp); > + } > + break; > + case AMDGPU_IRQ_STATE_ENABLE: > + /* MM HUB */ > + hub = &adev->vmhub[AMDGPU_MMHUB]; > + bits = hub->get_vm_protection_bits(); > + for (i = 0; i< 16; i++) { > + reg = hub->vm_context0_cntl + i; > + tmp = RREG32(reg); > + tmp |= bits; > + WREG32(reg, tmp); > + } > + > + /* GFX HUB */ > + hub = &adev->vmhub[AMDGPU_GFXHUB]; > + bits = hub->get_vm_protection_bits(); > + for (i = 0; i < 16; i++) { > + reg = hub->vm_context0_cntl + i; > + tmp = RREG32(reg); > + tmp |= bits; > + WREG32(reg, tmp); > + } > + break; > + default: > + break; > + } > + > + return 0; > + return 0; > +} > +
Probably only need one :-) Dave. _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx