and no need to insert 128 nops after gfx8 vm flush anymore
because there was double SWITCH_BUFFER append to vm flush

Change-Id: I6ecec95236bd1745f2beaa1b34a075748813f131
Signed-off-by: Monk Liu <monk....@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 29 ++++++++++++++++++-----------
 1 file changed, 18 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 396c075..3016e535 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6390,8 +6390,6 @@ static void gfx_v8_0_ring_emit_vm_flush(struct 
amdgpu_ring *ring,
                /* sync PFP to ME, otherwise we might get invalid PFP reads */
                amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
                amdgpu_ring_write(ring, 0x0);
-               /* GFX8 emits 128 dw nop to prevent CE access VM before 
vm_flush finish */
-               amdgpu_ring_insert_nop(ring, 128);
        }
 }
 
@@ -6791,15 +6789,24 @@ static const struct amdgpu_ring_funcs 
gfx_v8_0_ring_funcs_gfx = {
        .get_rptr = gfx_v8_0_ring_get_rptr,
        .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
        .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
-       .emit_frame_size =
-               20 + /* gfx_v8_0_ring_emit_gds_switch */
-               7 + /* gfx_v8_0_ring_emit_hdp_flush */
-               5 + /* gfx_v8_0_ring_emit_hdp_invalidate */
-               6 + 6 + 6 +/* gfx_v8_0_ring_emit_fence_gfx x3 for user fence, 
vm fence */
-               7 + /* gfx_v8_0_ring_emit_pipeline_sync */
-               128 + 19 + /* gfx_v8_0_ring_emit_vm_flush */
-               2 + /* gfx_v8_ring_emit_sb */
-               3 + 4 + 29, /* gfx_v8_ring_emit_cntxcntl including vgt 
flush/meta-data */
+       .emit_frame_size = /* maximum 215dw if count 16 IBs in */
+               5 +  /* COND_EXEC */
+               7 +  /* PIPELINE_SYNC */
+               19 + /* VM_FLUSH */
+               8 +  /* FENCE for VM_FLUSH */
+               20 + /* GDS switch */
+               4 + /* double SWITCH_BUFFER,
+                      the first COND_EXEC jump to the place just
+                          prior to this double SWITCH_BUFFER  */
+               5 + /* COND_EXEC */
+               7 +      /*     HDP_flush */
+               4 +      /*     VGT_flush */
+               14 + /* CE_META */
+               31 + /* DE_META */
+               3 + /* CNTX_CTRL */
+               5 + /* HDP_INVL */
+               8 + 8 + /* FENCE x2 */
+               2, /* SWITCH_BUFFER */
        .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */
        .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
        .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
-- 
2.7.4

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