[PATCH 02/10] drm/amd/amdgpu: cleanup gfx_v9_0_set_priv_inst_fault_state()

[Tom St Denis]

Use new WREG32_FIELD15 macro.

Signed-off-by: Tom St Denis <tom.stde...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 15 +++------------
 1 file changed, 3 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 3888743bc868..714fd0f228cf 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3473,21 +3473,12 @@ static int gfx_v9_0_set_priv_inst_fault_state(struct 
amdgpu_device *adev,
                                              unsigned type,
                                              enum amdgpu_interrupt_state state)
 {
-       u32 cp_int_cntl;
-
        switch (state) {
        case AMDGPU_IRQ_STATE_DISABLE:
-               cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, 
mmCP_INT_CNTL_RING0));
-               cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
-                                           PRIV_INSTR_INT_ENABLE, 0);
-               WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), 
cp_int_cntl);
-               break;
        case AMDGPU_IRQ_STATE_ENABLE:
-               cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, 
mmCP_INT_CNTL_RING0));
-               cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
-                                           PRIV_INSTR_INT_ENABLE, 1);
-               WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), 
cp_int_cntl);
-               break;
+               WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
+                              PRIV_INSTR_INT_ENABLE,
+                              state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
        default:
                break;
        }
-- 
2.12.0

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