> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Tom St Denis
> Sent: Monday, May 15, 2017 9:49 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: StDenis, Tom
> Subject: [PATCH 1/5] drm/amd/amdgpu: Clean up GFX6 tilemode
> programming
>
> Signed-off-by: Tom St Denis <tom.stde...@amd.com>
Patches 1-4 are:
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 1556 ++++++++++++++---------
> ----------
> 1 file changed, 676 insertions(+), 880 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 5d9e95bcd011..36a70e93b293 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -393,8 +393,11 @@ static int gfx_v6_0_init_microcode(struct
> amdgpu_device *adev)
>
> static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
> {
> - const u32 num_tile_mode_states = 32;
> - u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
> + const u32 num_tile_mode_states = ARRAY_SIZE(adev-
> >gfx.config.tile_mode_array);
> + u32 reg_offset, split_equal_to_row_size, *tilemode;
> +
> + memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev-
> >gfx.config.tile_mode_array));
> + tilemode = adev->gfx.config.tile_mode_array;
>
> switch (adev->gfx.config.mem_row_size_in_kb) {
> case 1:
> @@ -410,887 +413,680 @@ static void
> gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
> }
>
> if (adev->asic_type == CHIP_VERDE) {
> - for (reg_offset = 0; reg_offset < num_tile_mode_states;
> reg_offset++) {
> - switch (reg_offset) {
> - case 0:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 1:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 2:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 3:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_8_BANK) |
> -
> TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 4:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16));
> - break;
> - case 5:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - case 6:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - case 7:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - case 8:
> - gb_tile_moden =
> (ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
> - break;
> - case 9:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16));
> - break;
> - case 10:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 11:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 12:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 13:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16));
> - break;
> - case 14:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 15:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 16:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 17:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK) |
> -
> TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 18:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_1D_TILED_THICK) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16));
> - break;
> - case 19:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK) |
> -
> TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 20:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THICK) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK) |
> -
> TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 21:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_8_BANK));
> - break;
> - case 22:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_8_BANK));
> - break;
> - case 23:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - case 24:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - case 25:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - case 26:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - case 27:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - case 28:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - case 29:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - case 30:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - default:
> - continue;
> - }
> - adev->gfx.config.tile_mode_array[reg_offset] =
> gb_tile_moden;
> - WREG32(mmGB_TILE_MODE0 + reg_offset,
> gb_tile_moden);
> - }
> - } else if (adev->asic_type == CHIP_OLAND ||
> - adev->asic_type == CHIP_HAINAN) {
> - for (reg_offset = 0; reg_offset < num_tile_mode_states;
> reg_offset++) {
> - switch (reg_offset) {
> - case 0:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 1:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 2:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 3:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_8_BANK) |
> -
> TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 4:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2));
> - break;
> - case 5:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_8_BANK));
> - break;
> - case 6:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_8_BANK));
> - break;
> - case 7:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - case 8:
> - gb_tile_moden =
> (ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
> - break;
> - case 9:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2));
> - break;
> - case 10:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 11:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 12:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 13:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2));
> - break;
> - case 14:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 15:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 16:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 17:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK) |
> -
> TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 18:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_1D_TILED_THICK) |
> -
> PIPE_CONFIG(ADDR_SURF_P2));
> - break;
> - case 19:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK) |
> -
> TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 20:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THICK) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK) |
> -
> TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 21:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_8_BANK));
> - break;
> - case 22:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_8_BANK));
> - break;
> - case 23:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_8_BANK));
> - break;
> - case 24:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_8_BANK));
> - break;
> - case 25:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - case 26:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - case 27:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - case 28:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - case 29:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - case 30:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - default:
> - continue;
> - }
> - adev->gfx.config.tile_mode_array[reg_offset] =
> gb_tile_moden;
> - WREG32(mmGB_TILE_MODE0 + reg_offset,
> gb_tile_moden);
> - }
> + tilemode[0] =
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[1] =
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[2] =
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[3] =
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_8_BANK) |
> + TILE_SPLIT(split_equal_to_row_size);
> + tilemode[4] =
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16);
> + tilemode[5] =
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK);
> + tilemode[6] =
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK);
> + tilemode[7] =
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK);
> + tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
> + tilemode[9] =
> MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16);
> + tilemode[10] =
> MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[11] =
> MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[12] =
> MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[13] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16);
> + tilemode[14] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[15] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[16] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[17] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK) |
> + TILE_SPLIT(split_equal_to_row_size);
> + tilemode[18] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_1D_TILED_THICK) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16);
> + tilemode[19] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK) |
> + TILE_SPLIT(split_equal_to_row_size);
> + tilemode[20] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THICK) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK) |
> + TILE_SPLIT(split_equal_to_row_size);
> + tilemode[21] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_8_BANK);
> + tilemode[22] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_8_BANK);
> + tilemode[23] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK);
> + tilemode[24] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK);
> + tilemode[25] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK);
> + tilemode[26] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK);
> + tilemode[27] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK);
> + tilemode[28] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK);
> + tilemode[29] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK);
> + tilemode[30] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK);
> + for (reg_offset = 0; reg_offset < num_tile_mode_states;
> reg_offset++)
> + WREG32(mmGB_TILE_MODE0 + reg_offset,
> tilemode[reg_offset]);
> + } else if (adev->asic_type == CHIP_OLAND || adev->asic_type ==
> CHIP_HAINAN) {
> + tilemode[0] =
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[1] =
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[2] =
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[3] =
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_8_BANK) |
> + TILE_SPLIT(split_equal_to_row_size);
> + tilemode[4] =
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2);
> + tilemode[5] =
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_8_BANK);
> + tilemode[6] =
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_8_BANK);
> + tilemode[7] =
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK);
> + tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
> + tilemode[9] =
> MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2);
> + tilemode[10] =
> MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[11] =
> MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[12] =
> MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[13] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2);
> + tilemode[14] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[15] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[16] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[17] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK) |
> + TILE_SPLIT(split_equal_to_row_size);
> + tilemode[18] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_1D_TILED_THICK) |
> + PIPE_CONFIG(ADDR_SURF_P2);
> + tilemode[19] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK) |
> + TILE_SPLIT(split_equal_to_row_size);
> + tilemode[20] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THICK) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK) |
> + TILE_SPLIT(split_equal_to_row_size);
> + tilemode[21] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_8_BANK);
> + tilemode[22] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_8_BANK);
> + tilemode[23] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_8_BANK);
> + tilemode[24] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_8_BANK);
> + tilemode[25] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK);
> + tilemode[26] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK);
> + tilemode[27] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK);
> + tilemode[28] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK);
> + tilemode[29] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK);
> + tilemode[30] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK);
> + for (reg_offset = 0; reg_offset < num_tile_mode_states;
> reg_offset++)
> + WREG32(mmGB_TILE_MODE0 + reg_offset,
> tilemode[reg_offset]);
> } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type ==
> CHIP_PITCAIRN)) {
> - for (reg_offset = 0; reg_offset < num_tile_mode_states;
> reg_offset++) {
> - switch (reg_offset) {
> - case 0:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 1:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 2:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 3:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_4_BANK) |
> -
> TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 4:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
> - break;
> - case 5:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - case 6:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - case 7:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - case 8:
> - gb_tile_moden =
> (ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
> - break;
> - case 9:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
> - break;
> - case 10:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 11:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 12:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 13:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
> - break;
> - case 14:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 15:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 16:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 17:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK) |
> -
> TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 18:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_1D_TILED_THICK) |
> -
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
> - break;
> - case 19:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
> -
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK) |
> -
> TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 20:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THICK) |
> -
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK) |
> -
> TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 21:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - case 22:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - case 23:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - case 24:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - case 25:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - case 26:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - case 27:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - case 28:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - case 29:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - case 30:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - default:
> - continue;
> - }
> - adev->gfx.config.tile_mode_array[reg_offset] =
> gb_tile_moden;
> - WREG32(mmGB_TILE_MODE0 + reg_offset,
> gb_tile_moden);
> - }
> - } else{
> -
> + tilemode[0] =
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)
> |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[1] =
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)
> |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[2] =
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)
> |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[3] =
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)
> |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK) |
> + TILE_SPLIT(split_equal_to_row_size);
> + tilemode[4] =
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
> + tilemode[5] =
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)
> |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK);
> + tilemode[6] =
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)
> |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK);
> + tilemode[7] =
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK);
> + tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
> + tilemode[9] =
> MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
> + tilemode[10] =
> MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)
> |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[11] =
> MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)
> |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[12] =
> MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)
> |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[13] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
> + tilemode[14] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)
> |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[15] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)
> |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[16] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)
> |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_16_BANK);
> + tilemode[17] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)
> |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_16_BANK) |
> + TILE_SPLIT(split_equal_to_row_size);
> + tilemode[18] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_1D_TILED_THICK) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
> + tilemode[19] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)
> |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_16_BANK) |
> + TILE_SPLIT(split_equal_to_row_size);
> + tilemode[20] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THICK) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)
> |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_16_BANK) |
> + TILE_SPLIT(split_equal_to_row_size);
> + tilemode[21] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)
> |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK);
> + tilemode[22] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)
> |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK);
> + tilemode[23] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)
> |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK);
> + tilemode[24] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)
> |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK);
> + tilemode[25] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK);
> + tilemode[26] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK);
> + tilemode[27] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK);
> + tilemode[28] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK);
> + tilemode[29] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK);
> + tilemode[30] =
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)
> |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK);
> + for (reg_offset = 0; reg_offset < num_tile_mode_states;
> reg_offset++)
> + WREG32(mmGB_TILE_MODE0 + reg_offset,
> tilemode[reg_offset]);
> + } else {
> DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
> }
> -
> }
>
> static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32
> se_num,
> --
> 2.12.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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