From: Amber Lin <amber....@amd.com>

Set the system bit for foreign BO mappings and use the remote VRAM
BAR address as the VRAM base offset.

Signed-off-by: Amber Lin <amber....@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehl...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 1d1810d..5f08e81 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1582,6 +1582,7 @@ static int amdgpu_vm_bo_split_mapping(struct 
amdgpu_device *adev,
                                      dma_addr_t *pages_addr,
                                      struct amdgpu_vm *vm,
                                      struct amdgpu_bo_va_mapping *mapping,
+                                     uint64_t vram_base_offset,
                                      uint64_t flags,
                                      struct drm_mm_node *nodes,
                                      struct dma_fence **fence)
@@ -1640,7 +1641,7 @@ static int amdgpu_vm_bo_split_mapping(struct 
amdgpu_device *adev,
                                max_entries = min(max_entries, 16ull * 1024ull);
                        addr = 0;
                } else if (flags & AMDGPU_PTE_VALID) {
-                       addr += adev->vm_manager.vram_base_offset;
+                       addr += vram_base_offset;
                }
                addr += pfn << PAGE_SHIFT;
 
@@ -1685,6 +1686,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
        struct ttm_mem_reg *mem;
        struct drm_mm_node *nodes;
        struct dma_fence *exclusive;
+       uint64_t vram_base_offset = adev->vm_manager.vram_base_offset;
+       struct amdgpu_device *bo_adev;
        int r;
 
        if (clear || !bo_va->bo) {
@@ -1706,9 +1709,15 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
 
        if (bo_va->bo) {
                flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
+               bo_adev = amdgpu_ttm_adev(bo_va->bo->tbo.bdev);
                gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) &&
-                       adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ?
+                       adev == bo_adev) ?
                        flags : 0;
+               if (mem && mem->mem_type == TTM_PL_VRAM &&
+                       adev != bo_adev) {
+                       flags |= AMDGPU_PTE_SYSTEM;
+                       vram_base_offset = bo_adev->mc.aper_base;
+               }
        } else {
                flags = 0x0;
                gtt_flags = ~0x0;
@@ -1722,8 +1731,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
        list_for_each_entry(mapping, &bo_va->invalids, list) {
                r = amdgpu_vm_bo_split_mapping(adev, exclusive,
                                               gtt_flags, pages_addr, vm,
-                                              mapping, flags, nodes,
-                                              &bo_va->last_pt_update);
+                                              mapping, vram_base_offset, flags,
+                                              nodes, &bo_va->last_pt_update);
                if (r)
                        return r;
        }
-- 
1.9.1

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