On 11/28/23 10:52, Melissa Wen wrote:
Prepare to hook up color state log according to the DCN version.

v3:
- put functions in single line (Siqueira)

Signed-off-by: Melissa Wen <m...@igalia.com>
---
  .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c   | 26 +++++++++++++------
  1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index 2b8b8366538e..9b801488eb9d 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -282,19 +282,13 @@ static void dcn10_log_hubp_states(struct dc *dc, void 
*log_ctx)
        DTN_INFO("\n");
  }
-void dcn10_log_hw_state(struct dc *dc,
-       struct dc_log_buffer_ctx *log_ctx)
+static void dcn10_log_color_state(struct dc *dc,
+                                 struct dc_log_buffer_ctx *log_ctx)
  {
        struct dc_context *dc_ctx = dc->ctx;
        struct resource_pool *pool = dc->res_pool;
        int i;
- DTN_INFO_BEGIN();
-
-       dcn10_log_hubbub_state(dc, log_ctx);
-
-       dcn10_log_hubp_states(dc, log_ctx);
-
        DTN_INFO("DPP:    IGAM format  IGAM mode    DGAM mode    RGAM mode"
                        "  GAMUT mode  C11 C12   C13 C14   C21 C22   C23 C24   "
                        "C31 C32   C33 C34\n");
@@ -351,6 +345,22 @@ void dcn10_log_hw_state(struct dc *dc,
                                s.idle);
        }
        DTN_INFO("\n");
+}
+
+void dcn10_log_hw_state(struct dc *dc,
+                       struct dc_log_buffer_ctx *log_ctx)
+{
+       struct dc_context *dc_ctx = dc->ctx;
+       struct resource_pool *pool = dc->res_pool;
+       int i;
+
+       DTN_INFO_BEGIN();
+
+       dcn10_log_hubbub_state(dc, log_ctx);
+
+       dcn10_log_hubp_states(dc, log_ctx);
+
+       dcn10_log_color_state(dc, log_ctx);
DTN_INFO("OTG: v_bs v_be v_ss v_se vpol vmax vmin vmax_sel vmin_sel h_bs h_be h_ss h_se hpol htot vtot underflow blank_en\n");

Reviewed-by: Rodrigo Siqueira <rodrigo.sique...@amd.com>

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