[PATCH 2/2] drm/amd/pm: Use metric table for pcie speed/width

[Asad Kamal]

Report pcie link speed/width using metric table in case
of one vf & if pmfw support is available, else report directly from
registers in case of pf. Skip reporting it for other cases.

Signed-off-by: Asad Kamal <asad.ka...@amd.com>
---
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c   | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index 744c84f3029f..2a934864b5eb 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -2167,6 +2167,7 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct 
smu_context *smu, void **table
                (struct gpu_metrics_v1_5 *)smu_table->gpu_metrics_table;
        struct amdgpu_device *adev = smu->adev;
        int ret = 0, xcc_id, inst, i, j;
+       enum amdgpu_sriov_vf_mode mode;
        MetricsTableX_t *metrics_x;
        MetricsTableA_t *metrics_a;
        u16 link_width_level;
@@ -2229,7 +2230,17 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct 
smu_context *smu, void **table
        gpu_metrics->gfxclk_lock_status = GET_METRIC_FIELD(GfxLockXCDMak) >> 
GET_INST(GC, 0);
 
        if (!(adev->flags & AMD_IS_APU)) {
-               if (!amdgpu_sriov_vf(adev)) {
+               /*Check smu version, PCIE link speed and width will be reported 
from pmfw metric
+                * table for both pf & one vf for smu version 85.99.0 or higher 
else report only
+                * for pf from registers
+                */
+               mode = amdgpu_virt_get_sriov_vf_mode(adev);
+               if (smu->smc_fw_version >= 0x556300 &&
+                   mode != SRIOV_VF_MODE_MULTI_VF) {
+                       gpu_metrics->pcie_link_width = metrics_x->PCIeLinkWidth;
+                       gpu_metrics->pcie_link_speed =
+                               pcie_gen_to_speed(metrics_x->PCIeLinkSpeed);
+               } else if (!amdgpu_sriov_vf(adev)) {
                        link_width_level = 
smu_v13_0_6_get_current_pcie_link_width_level(smu);
                        if (link_width_level > MAX_LINK_WIDTH)
                                link_width_level = 0;
@@ -2239,6 +2250,7 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct 
smu_context *smu, void **table
                        gpu_metrics->pcie_link_speed =
                                smu_v13_0_6_get_current_pcie_link_speed(smu);
                }
+
                gpu_metrics->pcie_bandwidth_acc =
                                SMUQ10_ROUND(metrics_x->PcieBandwidthAcc[0]);
                gpu_metrics->pcie_bandwidth_inst =
-- 
2.42.0