Add offsets, mask and shift macros for IH v6.0
which are needed to configure ring1 client irq
redirection.

Signed-off-by: Sunil Khatri <sunil.kha...@amd.com>
---
 .../drm/amd/include/asic_reg/oss/osssys_6_0_0_offset.h |  4 ++++
 .../amd/include/asic_reg/oss/osssys_6_0_0_sh_mask.h    | 10 ++++++++++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_offset.h
index 8b931bbabe70..969e006b859b 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_offset.h
@@ -237,6 +237,10 @@
 #define regSEM_REGISTER_LAST_PART2_BASE_IDX                                    
                         0
 #define regIH_CLIENT_CFG                                                       
                         0x0184
 #define regIH_CLIENT_CFG_BASE_IDX                                              
                         0
+#define regIH_RING1_CLIENT_CFG_INDEX                                           
                         0x0185
+#define regIH_RING1_CLIENT_CFG_INDEX_BASE_IDX                                  
                         0
+#define regIH_RING1_CLIENT_CFG_DATA                                            
                         0x0186
+#define regIH_RING1_CLIENT_CFG_DATA_BASE_IDX                                   
                         0
 #define regIH_CLIENT_CFG_INDEX                                                 
                         0x0188
 #define regIH_CLIENT_CFG_INDEX_BASE_IDX                                        
                         0
 #define regIH_CLIENT_CFG_DATA                                                  
                         0x0189
diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_sh_mask.h
index f262f44fa68c..a672a91e58f0 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_sh_mask.h
@@ -888,6 +888,16 @@
 //IH_CLIENT_CFG
 #define IH_CLIENT_CFG__TOTAL_CLIENT_NUM__SHIFT                                 
                               0x0
 #define IH_CLIENT_CFG__TOTAL_CLIENT_NUM_MASK                                   
                               0x0000003FL
+//IH_RING1_CLIENT_CFG_INDEX
+#define IH_RING1_CLIENT_CFG_INDEX__INDEX__SHIFT                                
                               0x0
+#define IH_RING1_CLIENT_CFG_INDEX__INDEX_MASK                                  
                               0x00000007L
+//IH_RING1_CLIENT_CFG_DATA
+#define IH_RING1_CLIENT_CFG_DATA__CLIENT_ID__SHIFT                             
                               0x0
+#define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID__SHIFT                             
                               0x8
+#define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MATCH_ENABLE__SHIFT                
                               0x10
+#define IH_RING1_CLIENT_CFG_DATA__CLIENT_ID_MASK                               
                               0x000000FFL
+#define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MASK                               
                               0x0000FF00L
+#define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MATCH_ENABLE_MASK                  
                               0x00010000L
 //IH_CLIENT_CFG_INDEX
 #define IH_CLIENT_CFG_INDEX__INDEX__SHIFT                                      
                               0x0
 #define IH_CLIENT_CFG_INDEX__INDEX_MASK                                        
                               0x0000001FL
-- 
2.34.1

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