[PATCH 38/45] drm/amd/display: Limit clock assignments by size of clk tables

[Tom Chung]

From: Alex Hung <alex.h...@amd.com>

[WHAT & HOW]
Check clk table's array size to avoid out-of-bound memory accesses.

This fixes two OVERRUN issues reported by Coverity.

Reviewed-by: Harry Wentland <harry.wentl...@amd.com>
Acked-by: Tom Chung <chiahsuan.ch...@amd.com>
Signed-off-by: Alex Hung <alex.h...@amd.com>
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
index d146c35f6d60..a3bb46725b4f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
@@ -131,7 +131,7 @@ static void dcn401_init_single_clock(struct 
clk_mgr_internal *clk_mgr, PPCLK_e c
                *num_levels = ret & 0xFF;
 
        /* if the initial message failed, num_levels will be 0 */
-       for (i = 0; i < *num_levels; i++) {
+       for (i = 0; i < *num_levels && i < 
ARRAY_SIZE(clk_mgr->base.bw_params->clk_table.entries); i++) {
                *((unsigned int *)entry_i) = 
(dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
                entry_i += 
sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
        }
-- 
2.34.1