[PATCH 03/14] drm/amdgpu: add set_reg_remap callback for NBIO 7.0

[Alex Deucher]

This will be used to consolidate the register remap offset
configuration and fix  HDP flushes on systems non-4K pages.

Reviewed-by: Felix Kuehling <felix.kuehl...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index aa0326d00c724..3dd743ebbc02d 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -278,6 +278,20 @@ static void nbio_v7_0_init_registers(struct amdgpu_device 
*adev)
                        SOC15_REG_OFFSET(NBIO, 0, 
mmHDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
 }
 
+#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
+
+static void nbio_v7_0_set_reg_remap(struct amdgpu_device *adev)
+{
+       if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) {
+               adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
+               adev->rmmio_remap.bus_addr = adev->rmmio_base + 
MMIO_REG_HOLE_OFFSET;
+       } else {
+               adev->rmmio_remap.reg_offset =
+                       SOC15_REG_OFFSET(NBIO, 0, 
mmHDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
+               adev->rmmio_remap.bus_addr = 0;
+       }
+}
+
 const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
        .get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset,
        .get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset,
@@ -297,4 +311,5 @@ const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
        .ih_control = nbio_v7_0_ih_control,
        .init_registers = nbio_v7_0_init_registers,
        .remap_hdp_registers = nbio_v7_0_remap_hdp_registers,
+       .set_reg_remap = nbio_v7_0_set_reg_remap,
 };
-- 
2.44.0