This patch doesn't need and will update new patch.

Signed-off-by: Jesse Zhang <jesse.zh...@amd.com>
---
 .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c   | 32 +++----------------
 1 file changed, 5 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
index 36a49cfc22e4..8908bbb3ff1f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
@@ -835,20 +835,10 @@ static int renoir_force_clk_levels(struct smu_context 
*smu,
                ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, 
&max_freq);
                if (ret)
                        return ret;
-                /* =  0: min_freq
-                 * =  1: UMD_PSTATE_CLK
-                 * >= 2: max_freq
-                 */
-               ret = smu_cmn_send_smc_msg_with_param(smu, 
SMU_MSG_SetSoftMaxSocclkByFreq,
-                                                       soft_max_level == 0 ? 
min_freq :
-                                                       soft_max_level == 1 ? 
RENOIR_UMD_PSTATE_SOCCLK : max_freq,
-                                                       NULL);
+               ret = smu_cmn_send_smc_msg_with_param(smu, 
SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL);
                if (ret)
                        return ret;
-               ret = smu_cmn_send_smc_msg_with_param(smu, 
SMU_MSG_SetHardMinSocclkByFreq,
-                                                       soft_min_level == 0 ? 
min_freq :
-                                                       soft_min_level == 1 ? 
RENOIR_UMD_PSTATE_SOCCLK : max_freq,
-                                                       NULL);
+               ret = smu_cmn_send_smc_msg_with_param(smu, 
SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL);
                if (ret)
                        return ret;
                break;
@@ -860,21 +850,10 @@ static int renoir_force_clk_levels(struct smu_context 
*smu,
                ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, 
&max_freq);
                if (ret)
                        return ret;
-               /* mclk levels are in reverse order
-                * =  0: max_freq
-                * =  1: UMD_PSTATE_CLK
-                * >= 2: min_freq
-                */
-               ret = smu_cmn_send_smc_msg_with_param(smu, 
SMU_MSG_SetSoftMaxFclkByFreq,
-                                                       soft_max_level >= 2 ? 
min_freq :
-                                                       soft_max_level == 1 ? 
RENOIR_UMD_PSTATE_FCLK : max_freq,
-                                                       NULL);
+               ret = smu_cmn_send_smc_msg_with_param(smu, 
SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL);
                if (ret)
                        return ret;
-               ret = smu_cmn_send_smc_msg_with_param(smu, 
SMU_MSG_SetHardMinFclkByFreq,
-                                                       soft_min_level >= 2  ? 
min_freq :
-                                                       soft_min_level == 1 ? 
RENOIR_UMD_PSTATE_SOCCLK : max_freq,
-                                                       NULL);
+               ret = smu_cmn_send_smc_msg_with_param(smu, 
SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL);
                if (ret)
                        return ret;
                break;
@@ -953,8 +932,7 @@ static int renoir_set_performance_level(struct smu_context 
*smu,
                                        enum amd_dpm_forced_level level)
 {
        int ret = 0;
-       /* default mask is UMD PSTATE CLK */
-       uint32_t sclk_mask = 1, mclk_mask = 1, soc_mask = 1;
+       uint32_t sclk_mask, mclk_mask, soc_mask;
 
        switch (level) {
        case AMD_DPM_FORCED_LEVEL_HIGH:
-- 
2.25.1

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