[PATCH AUTOSEL 6.8 41/52] drm/amd/display: Fix DC mode screen flickering on DCN321

[Sasha Levin]

From: Leo Ma <hanghong...@amd.com>

[ Upstream commit ce649bd2d834db83ecc2756a362c9a1ec61658a5 ]

[Why && How]
Screen flickering saw on 4K@60 eDP with high refresh rate external
monitor when booting up in DC mode. DC Mode Capping is disabled
which caused wrong UCLK being used.

Reviewed-by: Alvin Lee <alvin.l...@amd.com>
Acked-by: Wayne Lin <wayne....@amd.com>
Signed-off-by: Leo Ma <hanghong...@amd.com>
Tested-by: Daniel Wheeler <daniel.whee...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Sasha Levin <sas...@kernel.org>
---
 .../amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c  | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index bbdbc78161a00..39c63565baa9a 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -696,8 +696,12 @@ static void dcn32_update_clocks(struct clk_mgr 
*clk_mgr_base,
                                         * since we calculate mode support 
based on softmax being the max UCLK
                                         * frequency.
                                         */
-                                       dcn32_smu_set_hard_min_by_freq(clk_mgr, 
PPCLK_UCLK,
-                                                       
dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
+                                       if 
(dc->debug.disable_dc_mode_overwrite) {
+                                               
dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, 
dc->clk_mgr->bw_params->max_memclk_mhz);
+                                               
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, 
dc->clk_mgr->bw_params->max_memclk_mhz);
+                                       } else
+                                               
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
+                                                               
dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
                                } else {
                                        dcn32_smu_set_hard_min_by_freq(clk_mgr, 
PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
                                }
@@ -730,8 +734,13 @@ static void dcn32_update_clocks(struct clk_mgr 
*clk_mgr_base,
                /* set UCLK to requested value if P-State switching is 
supported, or to re-enable P-State switching */
                if (clk_mgr_base->clks.p_state_change_support &&
                                (update_uclk || 
!clk_mgr_base->clks.prev_p_state_change_support) &&
-                               
!dc->work_arounds.clock_update_disable_mask.uclk)
+                               
!dc->work_arounds.clock_update_disable_mask.uclk) {
+                       if (dc->clk_mgr->dc_mode_softmax_enabled && 
dc->debug.disable_dc_mode_overwrite)
+                               dcn30_smu_set_hard_max_by_freq(clk_mgr, 
PPCLK_UCLK,
+                                               
max((int)dc->clk_mgr->bw_params->dc_mode_softmax_memclk, 
khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)));
+
                        dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, 
khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
+               }
 
                if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
                                clk_mgr_base->clks.num_ways > 
new_clocks->num_ways) {
-- 
2.43.0