From: Adam Nelson <adnel...@amd.com>
[WHY]
After a non-3dlut test the MPCC_MCM_3DLUT_MODE::MPCC_MCM_3DLUT_SIZE is
incorrect.
[HOW]
Add register write to make valid.
Acked-by: Alex Hung <alex.h...@amd.com>
Reviewed-by: Rodrigo Siqueira <rodrigo.sique...@amd.com>
Signed-off-by: Adam Nelson <adnel...@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.c | 8 ++++++++
drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.h | 5 +++++
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 3 +++
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 1 +
4 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.c
b/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.c
index d6c99c6c2b35..37ab5a4eefc7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.c
@@ -297,6 +297,13 @@ void mpc401_program_lut_read_write_control(struct mpc
*mpc, const enum MCM_LUT_I
}
}
+void mpc401_program_3dlut_size(struct mpc *mpc, bool is_17x17x17, int mpcc_id)
+{
+ struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);
+
+ REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE,
is_17x17x17 ? 0 : 1);
+}
+
static void program_gamut_remap(
struct mpc *mpc,
unsigned int mpcc_id,
@@ -615,6 +622,7 @@ static const struct mpc_funcs dcn401_mpc_funcs = {
.populate_lut = mpc401_populate_lut,
.program_lut_read_write_control = mpc401_program_lut_read_write_control,
.program_lut_mode = mpc401_program_lut_mode,
+ .program_3dlut_size = mpc401_program_3dlut_size,
};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.h
b/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.h
index a8ef67695757..af44054c2477 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.h
@@ -221,6 +221,11 @@ void mpc401_program_lut_read_write_control(
bool lut_bank_a,
int mpcc_id);
+void mpc401_program_3dlut_size(
+ struct mpc *mpc,
+ bool is_17x17x17,
+ int mpcc_id);
+
void mpc401_set_gamut_remap(
struct mpc *mpc,
int mpcc_id,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 3b74c4a9c2a8..5b87186598e6 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -478,6 +478,7 @@ void dcn401_populate_mcm_luts(struct dc *dc,
enum MCM_LUT_XABLE shaper_xable = MCM_LUT_DISABLE;
enum MCM_LUT_XABLE lut3d_xable = MCM_LUT_DISABLE;
enum MCM_LUT_XABLE lut1d_xable = MCM_LUT_DISABLE;
+ bool is_17x17x17 = true;
dcn401_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &shaper_xable,
&lut3d_xable, &lut1d_xable);
@@ -543,6 +544,8 @@ void dcn401_populate_mcm_luts(struct dc *dc,
mpc->funcs->program_lut_read_write_control(mpc,
MCM_LUT_3DLUT, lut_bank_a, mpcc_id);
if (mpc->funcs->program_lut_mode)
mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT,
lut3d_xable, lut_bank_a, mpcc_id);
+ if (mpc->funcs->program_3dlut_size)
+ mpc->funcs->program_3dlut_size(mpc, is_17x17x17,
mpcc_id);
if (hubp->funcs->hubp_program_3dlut_fl_addr)
hubp->funcs->hubp_program_3dlut_fl_addr(hubp,
mcm_luts.lut3d_data.gpu_mem_params.addr);
switch (mcm_luts.lut3d_data.gpu_mem_params.layout) {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
index dd786600668f..34cf8efc5cb9 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
@@ -576,6 +576,7 @@ struct mpc_funcs {
void (*program_lut_read_write_control)(struct mpc *mpc, const enum
MCM_LUT_ID id, bool lut_bank_a, int mpcc_id);
void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_ID id,
const enum MCM_LUT_XABLE xable,
bool lut_bank_a, int mpcc_id);
+ void (*program_3dlut_size)(struct mpc *mpc, bool is_17x17x17, int
mpcc_id);
};
#endif
--
2.34.1
