From: Dmytro Laktyushkin <dmytro.laktyush...@amd.com>
Change-Id: Iea5cddde246293d3b22b66eb7d3956b167767b3d
Signed-off-by: Dmytro Laktyushkin <dmytro.laktyush...@amd.com>
Reviewed-by: Jordan Lazare <jordan.laz...@amd.com>
Acked-by: Harry Wentland <harry.wentl...@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 8 ++---
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 41 ++++------------------
.../drm/amd/display/dc/dce120/dce120_resource.c | 17 +--------
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 22 +++---------
.../gpu/drm/amd/display/dc/dcn10/dcn10_transform.h | 23 ++++++------
drivers/gpu/drm/amd/display/dc/inc/resource.h | 1 +
6 files changed, 27 insertions(+), 85 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
index 4e3f4e5..f30cd4d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -781,11 +781,7 @@ struct display_clock *dce112_disp_clk_create(
return &clk_dce->base;
}
-struct display_clock *dce120_disp_clk_create(
- struct dc_context *ctx,
- const struct dce_disp_clk_registers *regs,
- const struct dce_disp_clk_shift *clk_shift,
- const struct dce_disp_clk_mask *clk_mask)
+struct display_clock *dce120_disp_clk_create(struct dc_context *ctx)
{
struct dce_disp_clk *clk_dce = dm_alloc(sizeof(*clk_dce));
struct dm_pp_clock_levels_with_voltage clk_level_info = {0};
@@ -800,7 +796,7 @@ struct display_clock *dce120_disp_clk_create(
sizeof(dce120_max_clks_by_state));
dce_disp_clk_construct(
- clk_dce, ctx, regs, clk_shift, clk_mask);
+ clk_dce, ctx, NULL, NULL, NULL);
clk_dce->base.funcs = &dce120_funcs;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
index 103e905..0e717e0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
@@ -31,55 +31,30 @@
#define CLK_COMMON_REG_LIST_DCE_BASE() \
.DPREFCLK_CNTL = mmDPREFCLK_CNTL, \
- .DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL, \
- .MASTER_COMM_DATA_REG1 = mmMASTER_COMM_DATA_REG1, \
- .MASTER_COMM_CMD_REG = mmMASTER_COMM_CMD_REG, \
- .MASTER_COMM_CNTL_REG = mmMASTER_COMM_CNTL_REG
+ .DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL
#define CLK_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
#define CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \
- CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh), \
- CLK_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
- CLK_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh)
-
-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-#define CLK_DCN10_REG_LIST()\
- SR(DPREFCLK_CNTL), \
- SR(DENTIST_DISPCLK_CNTL), \
- SR(MASTER_COMM_DATA_REG1), \
- SR(MASTER_COMM_CMD_REG), \
- SR(MASTER_COMM_CNTL_REG)
-#endif
-
-#define CLK_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \
- CLK_SF(DCCG_DFS_DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \
- CLK_SF(DCCG_DFS_DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER,
mask_sh), \
- CLK_SF(DCCG_DFS_MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
mask_sh), \
- CLK_SF(DCCG_DFS_MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh)
+ CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh)
#define CLK_REG_FIELD_LIST(type) \
type DPREFCLK_SRC_SEL; \
- type DENTIST_DPREFCLK_WDIVIDER; \
- type MASTER_COMM_CMD_REG_BYTE0; \
- type MASTER_COMM_INTERRUPT
+ type DENTIST_DPREFCLK_WDIVIDER;
struct dce_disp_clk_shift {
- CLK_REG_FIELD_LIST(uint8_t);
+ CLK_REG_FIELD_LIST(uint8_t)
};
struct dce_disp_clk_mask {
- CLK_REG_FIELD_LIST(uint32_t);
+ CLK_REG_FIELD_LIST(uint32_t)
};
struct dce_disp_clk_registers {
uint32_t DPREFCLK_CNTL;
uint32_t DENTIST_DISPCLK_CNTL;
- uint32_t MASTER_COMM_DATA_REG1;
- uint32_t MASTER_COMM_CMD_REG;
- uint32_t MASTER_COMM_CNTL_REG;
};
/* Array identifiers and count for the divider ranges.*/
@@ -155,11 +130,7 @@ struct display_clock *dce112_disp_clk_create(
const struct dce_disp_clk_shift *clk_shift,
const struct dce_disp_clk_mask *clk_mask);
-struct display_clock *dce120_disp_clk_create(
- struct dc_context *ctx,
- const struct dce_disp_clk_registers *regs,
- const struct dce_disp_clk_shift *clk_shift,
- const struct dce_disp_clk_mask *clk_mask);
+struct display_clock *dce120_disp_clk_create(struct dc_context *ctx);
void dce_disp_clk_destroy(struct display_clock **disp_clk);
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index ec48535..8248124 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -137,18 +137,6 @@ static const struct dce110_timing_generator_offsets
dce120_tg_offsets[] = {
* end *********************/
-static const struct dce_disp_clk_registers disp_clk_regs = {
- CLK_COMMON_REG_LIST_DCE_BASE()
-};
-
-static const struct dce_disp_clk_shift disp_clk_shift = {
- CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
-};
-
-static const struct dce_disp_clk_mask disp_clk_mask = {
- CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
-};
-
static const struct dce_dmcu_registers dmcu_regs = {
DMCU_DCE110_COMMON_REG_LIST()
};
@@ -904,10 +892,7 @@ static bool construct(
}
}
- pool->base.display_clock = dce120_disp_clk_create(ctx,
- &disp_clk_regs,
- &disp_clk_shift,
- &disp_clk_mask);
+ pool->base.display_clock = dce120_disp_clk_create(ctx);
if (pool->base.display_clock == NULL) {
dm_error("DC: failed to create display clock!\n");
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index eebaffc..a0dd75d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -136,17 +136,6 @@ enum dcn10_clk_src_array_id {
/* macros to expend register list macro defined in HW object header file
* end *********************/
-static const struct dce_disp_clk_registers disp_clk_regs = {
- CLK_DCN10_REG_LIST()
-};
-
-static const struct dce_disp_clk_shift disp_clk_shift = {
- CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
-};
-
-static const struct dce_disp_clk_mask disp_clk_mask = {
- CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
-};
static const struct dce_dmcu_registers dmcu_regs = {
DMCU_DCN10_REG_LIST()
@@ -317,7 +306,7 @@ static const struct dcn10_opp_mask opp_mask = {
#define tf_regs(id)\
[id] = {\
- TF_REG_LIST_DCN(id),\
+ TF_REG_LIST_DCN10(id),\
}
static const struct dcn_transform_registers tf_regs[] = {
@@ -328,11 +317,11 @@ static const struct dcn_transform_registers tf_regs[] = {
};
static const struct dcn_transform_shift tf_shift = {
- TF_REG_LIST_SH_MASK_DCN(__SHIFT)
+ TF_REG_LIST_SH_MASK_DCN10(__SHIFT)
};
static const struct dcn_transform_mask tf_mask = {
- TF_REG_LIST_SH_MASK_DCN(_MASK),
+ TF_REG_LIST_SH_MASK_DCN10(_MASK),
};
@@ -1338,10 +1327,7 @@ static bool construct(
}
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
- pool->base.display_clock = dce120_disp_clk_create(ctx,
- &disp_clk_regs,
- &disp_clk_shift,
- &disp_clk_mask);
+ pool->base.display_clock = dce120_disp_clk_create(ctx);
if (pool->base.display_clock == NULL) {
dm_error("DC: failed to create display clock!\n");
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h
index 7c0089d..cd312bd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h
@@ -58,7 +58,6 @@
SRI(DCSURF_SEC_VIEWPORT_START, HUBP, id), \
SRI(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \
SRI(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \
- SRI(CM_GAMUT_REMAP_CONTROL, CM, id), \
SRI(MPC_SIZE, DSCL, id), \
SRI(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \
SRI(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \
@@ -71,7 +70,10 @@
SRI(SCL_VERT_FILTER_INIT_C, DSCL, id), \
SRI(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id), \
SRI(RECOUT_START, DSCL, id), \
- SRI(RECOUT_SIZE, DSCL, id), \
+ SRI(RECOUT_SIZE, DSCL, id)
+
+#define TF_REG_LIST_DCN10(id) \
+ TF_REG_LIST_DCN(id), \
SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\
@@ -92,8 +94,6 @@
SRI(CM_COMB_C31_C32, CM, id),\
SRI(CM_COMB_C33_C34, CM, id)
-
-
#define TF_REG_LIST_SH_MASK_DCN(mask_sh)\
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh),\
@@ -103,11 +103,6 @@
TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_END, mask_sh),\
TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_START, mask_sh),\
TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_END, mask_sh),\
- TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh),\
- TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh),\
- TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_REDUCE_MODE, mask_sh),\
- TF_SF(DSCL0_LB_DATA_FORMAT, DYNAMIC_PIXEL_DEPTH, mask_sh),\
- TF_SF(DSCL0_LB_DATA_FORMAT, DITHER_EN, mask_sh),\
TF_SF(DSCL0_LB_DATA_FORMAT, INTERLEAVE_EN, mask_sh),\
TF_SF(DSCL0_LB_DATA_FORMAT, ALPHA_EN, mask_sh),\
TF_SF(DSCL0_LB_MEMORY_CTRL, MEMORY_CONFIG, mask_sh),\
@@ -172,7 +167,15 @@
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_FRAC_BOT_C,
mask_sh),\
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh),\
TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\
- TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh),\
+ TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh)
+
+#define TF_REG_LIST_SH_MASK_DCN10(mask_sh)\
+ TF_REG_LIST_SH_MASK_DCN(mask_sh),\
+ TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh),\
+ TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh),\
+ TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_REDUCE_MODE, mask_sh),\
+ TF_SF(DSCL0_LB_DATA_FORMAT, DYNAMIC_PIXEL_DEPTH, mask_sh),\
+ TF_SF(DSCL0_LB_DATA_FORMAT, DITHER_EN, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C11, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C12, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h
b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index 7cac24d..04e5fd1 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -42,6 +42,7 @@ struct resource_caps {
int num_audio;
int num_stream_encoder;
int num_pll;
+ int num_dwb;
};
struct resource_straps {
--
2.7.4
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