On Mon, Jul 08, 2024 at 04:29:07PM -0400, Hamza Mahfooz wrote:
> Hook up drm_crtc_set_vblank_offdelay() in amdgpu_dm, so that we can
> enable PSR more quickly for displays that support it.
>
> Signed-off-by: Hamza Mahfooz <hamza.mahf...@amd.com>
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 30 ++++++++++++++-----
> 1 file changed, 22 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index fdbc9b57a23d..ee6c31e9d3c4 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -8231,7 +8231,7 @@ static int amdgpu_dm_encoder_init(struct drm_device
> *dev,
>
> static void manage_dm_interrupts(struct amdgpu_device *adev,
> struct amdgpu_crtc *acrtc,
> - bool enable)
> + struct dm_crtc_state *acrtc_state)
> {
> /*
> * We have no guarantee that the frontend index maps to the same
> @@ -8239,12 +8239,25 @@ static void manage_dm_interrupts(struct amdgpu_device
> *adev,
> *
> * TODO: Use a different interrupt or check DC itself for the mapping.
> */
> - int irq_type =
> - amdgpu_display_crtc_idx_to_irq_type(
> - adev,
> - acrtc->crtc_id);
> + int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
> + acrtc->crtc_id);
> + struct dc_crtc_timing *timing;
> + int offdelay;
> +
> + if (acrtc_state) {
> + timing = &acrtc_state->stream->timing;
> +
> + /* at least 2 frames */
> + offdelay = 2000 / div64_u64(div64_u64((timing->pix_clk_100hz *
> + (uint64_t)100),
> + timing->v_total),
> + timing->h_total) + 1;
Yeah, _especially_ when you have a this short timeout your really have to
instead fix the vblank driver code properly so you can enable
vblank_disable_immediate. This is just cheating :-)
-Sima
> +
> + if (acrtc_state->stream->link->psr_settings.psr_version <
> + DC_PSR_VERSION_UNSUPPORTED &&
> + amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 5, 0))
> + drm_crtc_set_vblank_offdelay(&acrtc->base, offdelay);
>
> - if (enable) {
> drm_crtc_vblank_on(&acrtc->base);
> amdgpu_irq_get(
> adev,
> @@ -9319,7 +9332,7 @@ static void amdgpu_dm_commit_streams(struct
> drm_atomic_state *state,
> if (old_crtc_state->active &&
> (!new_crtc_state->active ||
> drm_atomic_crtc_needs_modeset(new_crtc_state))) {
> - manage_dm_interrupts(adev, acrtc, false);
> + manage_dm_interrupts(adev, acrtc, NULL);
> dc_stream_release(dm_old_crtc_state->stream);
> }
> }
> @@ -9834,7 +9847,8 @@ static void amdgpu_dm_atomic_commit_tail(struct
> drm_atomic_state *state)
> drm_atomic_crtc_needs_modeset(new_crtc_state))) {
> dc_stream_retain(dm_new_crtc_state->stream);
> acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
> - manage_dm_interrupts(adev, acrtc, true);
> + manage_dm_interrupts(adev, acrtc,
> + to_dm_crtc_state(new_crtc_state));
> }
> /* Handle vrr on->off / off->on transitions */
> amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
> dm_new_crtc_state);
> --
> 2.45.1
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
