From: Aurabindo Pillai <aurabindo.pil...@amd.com>
To enable mesa to use display dcc, DM should expose them in the
supported modifiers. Add the best (most efficient) modifiers first.
Reviewed-by: Rodrigo Siqueira <rodrigo.sique...@amd.com>
Signed-off-by: Jerry Zuo <jerry....@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pil...@amd.com>
---
.../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 29 ++++++++++++++++---
1 file changed, 25 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index 0320200dae94..dde4f1dda2e2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -689,12 +689,33 @@ static void amdgpu_dm_plane_add_gfx12_modifiers(struct
amdgpu_device *adev,
uint64_t **mods, uint64_t *size, uint64_t *capacity)
{
uint64_t ver = AMD_FMT_MOD | AMD_FMT_MOD_SET(TILE_VERSION,
AMD_FMT_MOD_TILE_VER_GFX12);
+ uint64_t mod_256k = ver | AMD_FMT_MOD_SET(TILE,
AMD_FMT_MOD_TILE_GFX12_256K_2D);
+ uint64_t mod_64k = ver | AMD_FMT_MOD_SET(TILE,
AMD_FMT_MOD_TILE_GFX12_64K_2D);
+ uint64_t mod_4k = ver | AMD_FMT_MOD_SET(TILE,
AMD_FMT_MOD_TILE_GFX12_4K_2D);
+ uint64_t mod_256b = ver | AMD_FMT_MOD_SET(TILE,
AMD_FMT_MOD_TILE_GFX12_256B_2D);
+ uint64_t dcc = ver | AMD_FMT_MOD_SET(DCC, 1);
+ uint8_t max_comp_block[] = {1, 0};
+ uint64_t max_comp_block_mod[2] = {0};
+ uint8_t i = 0;
+
+ /* With DCC: Best choice should be kept first. Hence, add all 256k
modifiers of different
+ * max compressed blocks first and then move on to the next smaller
sized layouts */
+ for (i = 0; i < 2; i++)
+ max_comp_block_mod[i] =
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_comp_block[i]);
+ for (i = 0; i < 2; i++)
+ amdgpu_dm_plane_add_modifier(mods, size, capacity, ver | dcc |
max_comp_block_mod[i] | mod_256k);
+ for (i = 0; i < 2; i++)
+ amdgpu_dm_plane_add_modifier(mods, size, capacity, ver | dcc |
max_comp_block_mod[i] | mod_64k);
+ for (i = 0; i < 2; i++)
+ amdgpu_dm_plane_add_modifier(mods, size, capacity, ver | dcc |
max_comp_block_mod[i] | mod_4k);
+ for (i = 0; i < 2; i++)
+ amdgpu_dm_plane_add_modifier(mods, size, capacity, ver | dcc |
max_comp_block_mod[i] | mod_256b);
/* Without DCC: */
- amdgpu_dm_plane_add_modifier(mods, size, capacity, ver |
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_256K_2D));
- amdgpu_dm_plane_add_modifier(mods, size, capacity, ver |
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_64K_2D));
- amdgpu_dm_plane_add_modifier(mods, size, capacity, ver |
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_4K_2D));
- amdgpu_dm_plane_add_modifier(mods, size, capacity, ver |
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_256B_2D));
+ amdgpu_dm_plane_add_modifier(mods, size, capacity, ver | mod_256k);
+ amdgpu_dm_plane_add_modifier(mods, size, capacity, ver | mod_64k);
+ amdgpu_dm_plane_add_modifier(mods, size, capacity, ver | mod_4k);
+ amdgpu_dm_plane_add_modifier(mods, size, capacity, ver | mod_256b);
amdgpu_dm_plane_add_modifier(mods, size, capacity,
DRM_FORMAT_MOD_LINEAR);
}
--
2.34.1
