On Sat, Aug 12, 2017 at 12:56 AM, Felix Kuehling <felix.kuehl...@amd.com> wrote: > kfd2kgd->address_watch_get_offset returns dword register offsets. > The divide-by-sizeof(uint32_t) is incorrect.
In amdgpu that's true, but in radeon that's incorrect. If you look at cik_reg.h in radeon driver, you will see the address of all TCP_WATCH_* registers is multiplied by 4, and that's why Yair originally divided the offset by sizeof(uint32_t). I think this patch should move the divide-by-sizeof operation into the radeon function instead of just deleting it from kfd_dbgdev.c. Oded > > Signed-off-by: Felix Kuehling <felix.kuehl...@amd.com> > --- > drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c | 8 -------- > 1 file changed, 8 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c > b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c > index 8b14a4e..faa0790 100644 > --- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c > @@ -442,8 +442,6 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev > *dbgdev, > i, > ADDRESS_WATCH_REG_CNTL); > > - aw_reg_add_dword /= sizeof(uint32_t); > - > packets_vec[0].bitfields2.reg_offset = > aw_reg_add_dword - > AMD_CONFIG_REG_BASE; > > @@ -455,8 +453,6 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev > *dbgdev, > i, > ADDRESS_WATCH_REG_ADDR_HI); > > - aw_reg_add_dword /= sizeof(uint32_t); > - > packets_vec[1].bitfields2.reg_offset = > aw_reg_add_dword - > AMD_CONFIG_REG_BASE; > packets_vec[1].reg_data[0] = addrHi.u32All; > @@ -467,8 +463,6 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev > *dbgdev, > i, > ADDRESS_WATCH_REG_ADDR_LO); > > - aw_reg_add_dword /= sizeof(uint32_t); > - > packets_vec[2].bitfields2.reg_offset = > aw_reg_add_dword - AMD_CONFIG_REG_BASE; > packets_vec[2].reg_data[0] = addrLo.u32All; > @@ -485,8 +479,6 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev > *dbgdev, > i, > ADDRESS_WATCH_REG_CNTL); > > - aw_reg_add_dword /= sizeof(uint32_t); > - > packets_vec[3].bitfields2.reg_offset = > aw_reg_add_dword - > AMD_CONFIG_REG_BASE; > packets_vec[3].reg_data[0] = cntl.u32All; > -- > 2.7.4 > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
