SPL_ASSERT() is actually SPL_ASSERT_WARN() according to the macro definition in drivers/gpu/drm/amd/display/dc/spl/spl_debug.h, just replace the macro name SPL_ASSERT() with explicit SPL_ASSERT_WARN() to avoid ambiguous.
Here is the one-line script: sed -i "s/\<SPL_ASSERT\>/SPL_ASSERT_WARN/g" `grep SPL_ASSERT -rwl drivers/gpu/drm/amd/display` This is in preparation to add SPL_ASSERT_BUG() in later patch to harden the callers of division functions, no functional change intended. Signed-off-by: Tiezhu Yang <[email protected]> --- drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 12 +++---- .../gpu/drm/amd/display/dc/spl/spl_debug.h | 6 ++-- .../drm/amd/display/dc/spl/spl_fixpt31_32.c | 32 +++++++++---------- .../drm/amd/display/dc/spl/spl_fixpt31_32.h | 12 +++---- 4 files changed, 31 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c index 73a65913cb12..664343102f46 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c @@ -146,7 +146,7 @@ static struct spl_rect calculate_mpc_slice_in_timing_active( mpc_rec.x = plane_clip_rec->x + mpc_rec.width * mpc_slice_idx; mpc_rec.height = plane_clip_rec->height; mpc_rec.y = plane_clip_rec->y; - SPL_ASSERT(mpc_slice_count == 1 || + SPL_ASSERT_WARN(mpc_slice_count == 1 || spl_in->basic_out.view_format != SPL_VIEW_3D_SIDE_BY_SIDE || mpc_rec.width % 2 == 0); @@ -159,7 +159,7 @@ static struct spl_rect calculate_mpc_slice_in_timing_active( } if (spl_in->basic_out.view_format == SPL_VIEW_3D_TOP_AND_BOTTOM) { - SPL_ASSERT(mpc_rec.height % 2 == 0); + SPL_ASSERT_WARN(mpc_rec.height % 2 == 0); mpc_rec.height /= 2; } return mpc_rec; @@ -666,7 +666,7 @@ static void spl_calculate_inits_and_viewports(struct spl_in *spl_in, } spl_scratch->scl_data.viewport.x += src.x; spl_scratch->scl_data.viewport.y += src.y; - SPL_ASSERT(src.x % vpc_div == 0 && src.y % vpc_div == 0); + SPL_ASSERT_WARN(src.x % vpc_div == 0 && src.y % vpc_div == 0); spl_scratch->scl_data.viewport_c.x += src.x / vpc_div; spl_scratch->scl_data.viewport_c.y += src.y / vpc_div; } @@ -679,7 +679,7 @@ static void spl_handle_3d_recout(struct spl_in *spl_in, struct spl_rect *recout) * This may break with rotation, good thing we aren't mixing hw rotation and 3d */ if (spl_in->basic_in.mpc_combine_v) { - SPL_ASSERT(spl_in->basic_in.rotation == SPL_ROTATION_ANGLE_0 || + SPL_ASSERT_WARN(spl_in->basic_in.rotation == SPL_ROTATION_ANGLE_0 || (spl_in->basic_out.view_format != SPL_VIEW_3D_TOP_AND_BOTTOM && spl_in->basic_out.view_format != SPL_VIEW_3D_SIDE_BY_SIDE)); if (spl_in->basic_out.view_format == SPL_VIEW_3D_TOP_AND_BOTTOM) @@ -1052,7 +1052,7 @@ static bool spl_get_optimal_number_of_taps( *enable_easf_v = true; *enable_easf_h = true; } - SPL_ASSERT((spl_scratch->scl_data.taps.v_taps > 1) && + SPL_ASSERT_WARN((spl_scratch->scl_data.taps.v_taps > 1) && (spl_scratch->scl_data.taps.v_taps_c > 1)); } else { /* RGB */ if (spl_scratch->scl_data.taps.h_taps <= 3) { @@ -1065,7 +1065,7 @@ static bool spl_get_optimal_number_of_taps( *enable_easf_v = true; *enable_easf_h = true; } - SPL_ASSERT(spl_scratch->scl_data.taps.v_taps > 1); + SPL_ASSERT_WARN(spl_scratch->scl_data.taps.v_taps > 1); } } else { *enable_easf_v = false; diff --git a/drivers/gpu/drm/amd/display/dc/spl/spl_debug.h b/drivers/gpu/drm/amd/display/dc/spl/spl_debug.h index a6f6132df241..f01c932d550d 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/spl_debug.h +++ b/drivers/gpu/drm/amd/display/dc/spl/spl_debug.h @@ -20,11 +20,11 @@ #endif /* CONFIG_HAVE_KGDB || CONFIG_KGDB */ #if defined(CONFIG_DEBUG_KERNEL_DC) -#define SPL_ASSERT(expr) SPL_ASSERT_CRITICAL(expr) +#define SPL_ASSERT_WARN(expr) SPL_ASSERT_CRITICAL(expr) #else -#define SPL_ASSERT(expr) WARN_ON(!(expr)) +#define SPL_ASSERT_WARN(expr) WARN_ON(!(expr)) #endif /* CONFIG_DEBUG_KERNEL_DC */ -#define SPL_BREAK_TO_DEBUGGER() SPL_ASSERT(0) +#define SPL_BREAK_TO_DEBUGGER() SPL_ASSERT_WARN(0) #endif // SPL_DEBUG_H diff --git a/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.c b/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.c index 131f1e3949d3..07a5c09b250e 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.c +++ b/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.c @@ -29,7 +29,7 @@ static inline unsigned long long spl_complete_integer_division_u64( { unsigned long long result; - SPL_ASSERT(divisor); + SPL_ASSERT_WARN(divisor); result = spl_div64_u64_rem(dividend, divisor, remainder); @@ -63,7 +63,7 @@ struct spl_fixed31_32 spl_fixpt_from_fraction(long long numerator, long long den unsigned long long res_value = spl_complete_integer_division_u64( arg1_value, arg2_value, &remainder); - SPL_ASSERT(res_value <= (unsigned long long)LONG_MAX); + SPL_ASSERT_WARN(res_value <= (unsigned long long)LONG_MAX); /* determine fractional part */ { @@ -85,7 +85,7 @@ struct spl_fixed31_32 spl_fixpt_from_fraction(long long numerator, long long den { unsigned long long summand = (remainder << 1) >= arg2_value; - SPL_ASSERT(res_value <= (unsigned long long)LLONG_MAX - summand); + SPL_ASSERT_WARN(res_value <= (unsigned long long)LLONG_MAX - summand); res_value += summand; } @@ -118,19 +118,19 @@ struct spl_fixed31_32 spl_fixpt_mul(struct spl_fixed31_32 arg1, struct spl_fixed res.value = arg1_int * arg2_int; - SPL_ASSERT(res.value <= (long long)LONG_MAX); + SPL_ASSERT_WARN(res.value <= (long long)LONG_MAX); res.value <<= FIXED31_32_BITS_PER_FRACTIONAL_PART; tmp = arg1_int * arg2_fra; - SPL_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + SPL_ASSERT_WARN(tmp <= (unsigned long long)(LLONG_MAX - res.value)); res.value += tmp; tmp = arg2_int * arg1_fra; - SPL_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + SPL_ASSERT_WARN(tmp <= (unsigned long long)(LLONG_MAX - res.value)); res.value += tmp; @@ -139,7 +139,7 @@ struct spl_fixed31_32 spl_fixpt_mul(struct spl_fixed31_32 arg1, struct spl_fixed tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) + (tmp >= (unsigned long long)spl_fixpt_half.value); - SPL_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + SPL_ASSERT_WARN(tmp <= (unsigned long long)(LLONG_MAX - res.value)); res.value += tmp; @@ -163,17 +163,17 @@ struct spl_fixed31_32 spl_fixpt_sqr(struct spl_fixed31_32 arg) res.value = arg_int * arg_int; - SPL_ASSERT(res.value <= (long long)LONG_MAX); + SPL_ASSERT_WARN(res.value <= (long long)LONG_MAX); res.value <<= FIXED31_32_BITS_PER_FRACTIONAL_PART; tmp = arg_int * arg_fra; - SPL_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + SPL_ASSERT_WARN(tmp <= (unsigned long long)(LLONG_MAX - res.value)); res.value += tmp; - SPL_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + SPL_ASSERT_WARN(tmp <= (unsigned long long)(LLONG_MAX - res.value)); res.value += tmp; @@ -182,7 +182,7 @@ struct spl_fixed31_32 spl_fixpt_sqr(struct spl_fixed31_32 arg) tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) + (tmp >= (unsigned long long)spl_fixpt_half.value); - SPL_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + SPL_ASSERT_WARN(tmp <= (unsigned long long)(LLONG_MAX - res.value)); res.value += tmp; @@ -196,7 +196,7 @@ struct spl_fixed31_32 spl_fixpt_recip(struct spl_fixed31_32 arg) * Good idea to use Newton's method */ - SPL_ASSERT(arg.value); + SPL_ASSERT_WARN(arg.value); return spl_fixpt_from_fraction( spl_fixpt_one.value, @@ -295,7 +295,7 @@ static struct spl_fixed31_32 spl_fixed31_32_exp_from_taylor_series(struct spl_fi n + 1); /* TODO find correct res */ - SPL_ASSERT(spl_fixpt_lt(arg, spl_fixpt_one)); + SPL_ASSERT_WARN(spl_fixpt_lt(arg, spl_fixpt_one)); do res = spl_fixpt_add( @@ -337,9 +337,9 @@ struct spl_fixed31_32 spl_fixpt_exp(struct spl_fixed31_32 arg) spl_fixpt_ln2, m)); - SPL_ASSERT(m != 0); + SPL_ASSERT_WARN(m != 0); - SPL_ASSERT(spl_fixpt_lt( + SPL_ASSERT_WARN(spl_fixpt_lt( spl_fixpt_abs(r), spl_fixpt_one)); @@ -364,7 +364,7 @@ struct spl_fixed31_32 spl_fixpt_log(struct spl_fixed31_32 arg) struct spl_fixed31_32 error; - SPL_ASSERT(arg.value > 0); + SPL_ASSERT_WARN(arg.value > 0); /* TODO if arg is negative, return NaN */ /* TODO if arg is zero, return -INF */ diff --git a/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.h b/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.h index ed2647f9a099..b285f4397f07 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.h +++ b/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.h @@ -191,7 +191,7 @@ static inline struct spl_fixed31_32 spl_fixpt_clamp( */ static inline struct spl_fixed31_32 spl_fixpt_shl(struct spl_fixed31_32 arg, unsigned char shift) { - SPL_ASSERT(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) || + SPL_ASSERT_WARN(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) || ((arg.value < 0) && (arg.value >= ~(LLONG_MAX >> shift)))); arg.value = arg.value << shift; @@ -228,7 +228,7 @@ static inline struct spl_fixed31_32 spl_fixpt_add(struct spl_fixed31_32 arg1, st { struct spl_fixed31_32 res; - SPL_ASSERT(((arg1.value >= 0) && (LLONG_MAX - arg1.value >= arg2.value)) || + SPL_ASSERT_WARN(((arg1.value >= 0) && (LLONG_MAX - arg1.value >= arg2.value)) || ((arg1.value < 0) && (LLONG_MIN - arg1.value <= arg2.value))); res.value = arg1.value + arg2.value; @@ -253,7 +253,7 @@ static inline struct spl_fixed31_32 spl_fixpt_sub(struct spl_fixed31_32 arg1, st { struct spl_fixed31_32 res; - SPL_ASSERT(((arg2.value >= 0) && (LLONG_MIN + arg2.value <= arg1.value)) || + SPL_ASSERT_WARN(((arg2.value >= 0) && (LLONG_MIN + arg2.value <= arg1.value)) || ((arg2.value < 0) && (LLONG_MAX + arg2.value >= arg1.value))); res.value = arg1.value - arg2.value; @@ -445,7 +445,7 @@ static inline int spl_fixpt_round(struct spl_fixed31_32 arg) const long long summand = spl_fixpt_half.value; - SPL_ASSERT(LLONG_MAX - (long long)arg_value >= summand); + SPL_ASSERT_WARN(LLONG_MAX - (long long)arg_value >= summand); arg_value += summand; @@ -466,7 +466,7 @@ static inline int spl_fixpt_ceil(struct spl_fixed31_32 arg) const long long summand = spl_fixpt_one.value - spl_fixpt_epsilon.value; - SPL_ASSERT(LLONG_MAX - (long long)arg_value >= summand); + SPL_ASSERT_WARN(LLONG_MAX - (long long)arg_value >= summand); arg_value += summand; @@ -501,7 +501,7 @@ static inline struct spl_fixed31_32 spl_fixpt_truncate(struct spl_fixed31_32 arg bool negative = arg.value < 0; if (frac_bits >= FIXED31_32_BITS_PER_FRACTIONAL_PART) { - SPL_ASSERT(frac_bits == FIXED31_32_BITS_PER_FRACTIONAL_PART); + SPL_ASSERT_WARN(frac_bits == FIXED31_32_BITS_PER_FRACTIONAL_PART); return arg; } -- 2.42.0
