Add some HDCP related register headers for future use.
Signed-off-by: Aurabindo Pillai <[email protected]>
---
.../include/asic_reg/dcn/dcn_4_1_0_offset.h | 26 +++++++++++++++++++
.../include/asic_reg/dcn/dcn_4_1_0_sh_mask.h | 16 ++++++++++++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_offset.h
index 15e5a65cf492..70ee6be94a9b 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_offset.h
@@ -9776,6 +9776,14 @@
#define regDIG0_DIG_BE_CNTL_BASE_IDX
2
#define regDIG0_DIG_BE_EN_CNTL
0x20bd
#define regDIG0_DIG_BE_EN_CNTL_BASE_IDX
2
+#define regDIG0_HDCP_INT_CONTROL
0x20c0
+#define regDIG0_HDCP_INT_CONTROL_BASE_IDX
2
+#define regDIG0_HDCP_LINK0_STATUS
0x20c1
+#define regDIG0_HDCP_LINK0_STATUS_BASE_IDX
2
+#define regDIG0_HDCP_I2C_CONTROL_0
0x20c2
+#define regDIG0_HDCP_I2C_CONTROL_0_BASE_IDX
2
+#define regDIG0_HDCP_I2C_CONTROL_1
0x20c3
+#define regDIG0_HDCP_I2C_CONTROL_1_BASE_IDX
2
#define regDIG0_TMDS_CNTL
0x20e4
#define regDIG0_TMDS_CNTL_BASE_IDX
2
#define regDIG0_TMDS_CONTROL_CHAR
0x20e5
@@ -10081,6 +10089,12 @@
#define regDIG1_DIG_BE_CNTL_BASE_IDX
2
#define regDIG1_DIG_BE_EN_CNTL
0x21e1
#define regDIG1_DIG_BE_EN_CNTL_BASE_IDX
2
+#define regDIG1_HDCP_INT_CONTROL
0x21e4
+#define regDIG1_HDCP_INT_CONTROL_BASE_IDX
2
+#define regDIG1_HDCP_I2C_CONTROL_0
0x21e6
+#define regDIG1_HDCP_I2C_CONTROL_0_BASE_IDX
2
+#define regDIG1_HDCP_I2C_CONTROL_1
0x21e7
+#define regDIG1_HDCP_I2C_CONTROL_1_BASE_IDX
2
#define regDIG1_TMDS_CNTL
0x2208
#define regDIG1_TMDS_CNTL_BASE_IDX
2
#define regDIG1_TMDS_CONTROL_CHAR
0x2209
@@ -10386,6 +10400,12 @@
#define regDIG2_DIG_BE_CNTL_BASE_IDX
2
#define regDIG2_DIG_BE_EN_CNTL
0x2305
#define regDIG2_DIG_BE_EN_CNTL_BASE_IDX
2
+#define regDIG2_HDCP_INT_CONTROL
0x2308
+#define regDIG2_HDCP_INT_CONTROL_BASE_IDX
2
+#define regDIG2_HDCP_I2C_CONTROL_0
0x230a
+#define regDIG2_HDCP_I2C_CONTROL_0_BASE_IDX
2
+#define regDIG2_HDCP_I2C_CONTROL_1
0x230b
+#define regDIG2_HDCP_I2C_CONTROL_1_BASE_IDX
2
#define regDIG2_TMDS_CNTL
0x232c
#define regDIG2_TMDS_CNTL_BASE_IDX
2
#define regDIG2_TMDS_CONTROL_CHAR
0x232d
@@ -10691,6 +10711,12 @@
#define regDIG3_DIG_BE_CNTL_BASE_IDX
2
#define regDIG3_DIG_BE_EN_CNTL
0x2429
#define regDIG3_DIG_BE_EN_CNTL_BASE_IDX
2
+#define regDIG3_HDCP_INT_CONTROL
0x242c
+#define regDIG3_HDCP_INT_CONTROL_BASE_IDX
2
+#define regDIG3_HDCP_I2C_CONTROL_0
0x242e
+#define regDIG3_HDCP_I2C_CONTROL_0_BASE_IDX
2
+#define regDIG3_HDCP_I2C_CONTROL_1
0x242f
+#define regDIG3_HDCP_I2C_CONTROL_1_BASE_IDX
2
#define regDIG3_TMDS_CNTL
0x2450
#define regDIG3_TMDS_CNTL_BASE_IDX
2
#define regDIG3_TMDS_CONTROL_CHAR
0x2451
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h
b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h
index 5d9d5fea6e06..e3d841b2e9af 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h
@@ -2847,6 +2847,14 @@
#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP0_AUTH_FAIL_INTERRUPT_DEST__SHIFT
0x1
#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP0_I2C_XFER_REQ_INTERRUPT_DEST__SHIFT
0x2
#define
HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP0_I2C_XFER_DONE_INTERRUPT_DEST__SHIFT
0x3
+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP1_AUTH_SUCCESS_INTERRUPT_DEST__SHIFT
0x4
+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP1_AUTH_FAIL_INTERRUPT_DEST__SHIFT
0x5
+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP1_I2C_XFER_REQ_INTERRUPT_DEST__SHIFT
0x6
+#define
HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP1_I2C_XFER_DONE_INTERRUPT_DEST__SHIFT
0x7
+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP2_AUTH_SUCCESS_INTERRUPT_DEST__SHIFT
0x8
+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP2_AUTH_FAIL_INTERRUPT_DEST__SHIFT
0x9
+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP2_I2C_XFER_REQ_INTERRUPT_DEST__SHIFT
0xa
+#define
HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP2_I2C_XFER_DONE_INTERRUPT_DEST__SHIFT
0xb
#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP3_AUTH_SUCCESS_INTERRUPT_DEST__SHIFT
0xc
#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP3_AUTH_FAIL_INTERRUPT_DEST__SHIFT
0xd
#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP3_I2C_XFER_REQ_INTERRUPT_DEST__SHIFT
0xe
@@ -2871,6 +2879,14 @@
#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP0_AUTH_FAIL_INTERRUPT_DEST_MASK
0x00000002L
#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP0_I2C_XFER_REQ_INTERRUPT_DEST_MASK
0x00000004L
#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP0_I2C_XFER_DONE_INTERRUPT_DEST_MASK
0x00000008L
+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP1_AUTH_SUCCESS_INTERRUPT_DEST_MASK
0x00000010L
+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP1_AUTH_FAIL_INTERRUPT_DEST_MASK
0x00000020L
+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP1_I2C_XFER_REQ_INTERRUPT_DEST_MASK
0x00000040L
+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP1_I2C_XFER_DONE_INTERRUPT_DEST_MASK
0x00000080L
+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP2_AUTH_SUCCESS_INTERRUPT_DEST_MASK
0x00000100L
+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP2_AUTH_FAIL_INTERRUPT_DEST_MASK
0x00000200L
+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP2_I2C_XFER_REQ_INTERRUPT_DEST_MASK
0x00000400L
+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP2_I2C_XFER_DONE_INTERRUPT_DEST_MASK
0x00000800L
#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP3_AUTH_SUCCESS_INTERRUPT_DEST_MASK
0x00001000L
#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP3_AUTH_FAIL_INTERRUPT_DEST_MASK
0x00002000L
#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP3_I2C_XFER_REQ_INTERRUPT_DEST_MASK
0x00004000L
--
2.49.0
