[Public]
The patches 1-4 introduce userq VA tracking, and patches 5-6 add userq VA
validation.
Together, patches 1-6 provide full userq VA validation support. If there are no
objections,
I'll push the full series today to complete the implementation.
Regards,
Prike
> -----Original Message-----
> From: amd-gfx <[email protected]> On Behalf Of Liang,
> Prike
> Sent: Tuesday, September 30, 2025 4:20 PM
> To: [email protected]
> Cc: Deucher, Alexander <[email protected]>; Koenig, Christian
> <[email protected]>
> Subject: RE: [PATCH v5 4/8] drm/amdgpu: keeping waiting userq fence infinitely
>
> [Public]
>
> Hi Alex,
>
> Apologies for overlooking your earlier review comments. I just see patches
> 1-4 have
> already been reviewed. Can we proceed to land the series (patches 1-6) in drm-
> next?
>
> Regards,
> Prike
>
> > -----Original Message-----
> > From: Liang, Prike <[email protected]>
> > Sent: Monday, September 29, 2025 4:10 PM
> > To: [email protected]
> > Cc: Deucher, Alexander <[email protected]>; Koenig, Christian
> > <[email protected]>; Liang, Prike <[email protected]>
> > Subject: [PATCH v5 4/8] drm/amdgpu: keeping waiting userq fence
> > infinitely
> >
> > Keeping waiting the userq fence infinitely until hang detection, and
> > then suspend the hang queue and set the fence error.
> >
> > Signed-off-by: Prike Liang <[email protected]>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 11 ++++++++---
> > 1 file changed, 8 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
> > index a82b8d30228d..93d92b6ea86c 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
> > @@ -232,7 +232,7 @@ amdgpu_userq_map_helper(struct amdgpu_userq_mgr
> > *uq_mgr,
> > return r;
> > }
> >
> > -static void
> > +static int
> > amdgpu_userq_wait_for_last_fence(struct amdgpu_userq_mgr *uq_mgr,
> > struct amdgpu_usermode_queue *queue) {
> > @@ -
> > 240,11 +240,16 @@ amdgpu_userq_wait_for_last_fence(struct
> > amdgpu_userq_mgr *uq_mgr,
> > int ret;
> >
> > if (f && !dma_fence_is_signaled(f)) {
> > - ret = dma_fence_wait_timeout(f, true, msecs_to_jiffies(100));
> > - if (ret <= 0)
> > + ret = dma_fence_wait_timeout(f, true, MAX_SCHEDULE_TIMEOUT);
> > + if (ret <= 0) {
> > drm_file_err(uq_mgr->file, "Timed out waiting
> > for fence=%llu:%llu\n",
> > f->context, f->seqno);
> > + queue->state = AMDGPU_USERQ_STATE_HUNG;
> > + return -ETIME;
> > + }
> > }
> > +
> > + return ret;
> > }
> >
> > static void
> > --
> > 2.34.1
