[PATCH 1/3] drm/amd/pm: export a function amdgpu_smu_ras_send_msg to allow send msg directly

[YiPeng Chai]

provide a interface that allows ras client send msg to smu/pmfw directly.

Signed-off-by: Yang Wang <kevinyang.w...@amd.com>
Reviewed-by: Tao Zhou <tao.zh...@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c     | 11 +++++++++++
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 11 +++++++++++
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c  | 19 +++++++++++++++++++
 3 files changed, 41 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index fb8086859857..6cda01ce6a64 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -609,6 +609,17 @@ bool is_support_cclk_dpm(struct amdgpu_device *adev)
        return true;
 }
 
+int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type 
msg,
+                           uint32_t param, uint32_t *read_arg)
+{
+       struct smu_context *smu = adev->powerplay.pp_handle;
+       int ret = -EOPNOTSUPP;
+
+       if (smu->ppt_funcs && smu->ppt_funcs->ras_send_msg)
+               ret = smu->ppt_funcs->ras_send_msg(smu, msg, param, read_arg);
+
+       return ret;
+}
 
 static int smu_sys_get_pp_table(void *handle,
                                char **table)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 582c186d8b62..87d855b76e61 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -1521,6 +1521,15 @@ struct pptable_funcs {
         */
        ssize_t (*get_xcp_metrics)(struct smu_context *smu, int xcp_id,
                                   void *table);
+       /**
+        * @ras_send_msg: Send a message with a parameter from Ras
+        * &msg: Type of message.
+        * &param: Message parameter.
+        * &read_arg: SMU response (optional).
+        */
+       int (*ras_send_msg)(struct smu_context *smu,
+                           enum smu_message_type msg, uint32_t param, uint32_t 
*read_arg);
+
 };
 
 typedef enum {
@@ -1786,6 +1795,8 @@ int smu_set_pm_policy(struct smu_context *smu, enum 
pp_pm_policy p_type,
 ssize_t smu_get_pm_policy_info(struct smu_context *smu,
                               enum pp_pm_policy p_type, char *sysbuf);
 
+int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type 
msg,
+                           uint32_t param, uint32_t *readarg);
 #endif
 
 void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id 
fea_id);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index cbe5b06438c1..126efdbc0f02 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -3227,6 +3227,24 @@ static int smu_v13_0_6_reset_vcn(struct smu_context 
*smu, uint32_t inst_mask)
        return ret;
 }
 
+static int smu_v13_0_6_ras_send_msg(struct smu_context *smu, enum 
smu_message_type msg, uint32_t param, uint32_t *read_arg)
+{
+       int ret;
+
+       switch (msg) {
+       case SMU_MSG_QueryValidMcaCount:
+       case SMU_MSG_QueryValidMcaCeCount:
+       case SMU_MSG_McaBankDumpDW:
+       case SMU_MSG_McaBankCeDumpDW:
+       case SMU_MSG_ClearMcaOnRead:
+               ret = smu_cmn_send_smc_msg_with_param(smu, msg, param, 
read_arg);
+               break;
+       default:
+               ret = -EPERM;
+       }
+
+       return ret;
+}
 
 static int smu_v13_0_6_post_init(struct smu_context *smu)
 {
@@ -3922,6 +3940,7 @@ static const struct pptable_funcs smu_v13_0_6_ppt_funcs = 
{
        .reset_sdma = smu_v13_0_6_reset_sdma,
        .dpm_reset_vcn = smu_v13_0_6_reset_vcn,
        .post_init = smu_v13_0_6_post_init,
+       .ras_send_msg = smu_v13_0_6_ras_send_msg,
 };
 
 void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu)
-- 
2.34.1