On 26.09.25 20:26, Timur Kristóf wrote:
> Set stricter dividers to stabilize the PLL's feedback loop.
> In practice, the actual output isn't exactly the target
> clock, but slowly oscillates around it. This makes it
> more stable.
>
> The values here are taken from the non-DC code.
There are also a bunch of other restrictions which need to be kept in mind.
For example what is the minimum feedback divider value the DC code uses?
We once had a longer discussion with the PLL HW engineers to get this working
because at least the display code we used as reference back then got it wrong.
Regards,
Christian.
>
> Signed-off-by: Timur Kristóf <[email protected]>
> ---
> drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> index b4f5b4a6331a..00f25e2ee081 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> @@ -1700,6 +1700,13 @@ bool dce110_clk_src_construct(
> clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
> calc_pll_cs_init_data.min_pll_ref_divider = 1;
> calc_pll_cs_init_data.max_pll_ref_divider =
> clk_src->cs_mask->PLL_REF_DIV;
> +
> + if (ctx->dce_version <= DCE_VERSION_10_0) {
> + /* Set stricter dividers to stabilize the PLL's feedback loop
> on old HW. */
> + calc_pll_cs_init_data.min_pix_clk_pll_post_divider = 2;
> + calc_pll_cs_init_data.min_pll_ref_divider = 2;
> + }
> +
> /* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
> calc_pll_cs_init_data.min_override_input_pxl_clk_pll_freq_khz = 0;
> /* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
