On 11/6/25 19:44, Timur Kristóf wrote: > Sometimes the VCE PLL times out waiting for CTLACK/CTLACK2. > When it happens, the VCE still works, but much slower. > Observed on a Tahiti GPU, but not all: > - FirePro W9000 has the issue > - Radeon R9 280X not affected > - Radeon HD 7990 not affected > > As a workaround, on the affected chip just don't put the > VCE PLL in sleep mode. Leaving the VCE PLL in bypass mode > or reset mode both work. Using bypass mode is simpler. > > Signed-off-by: Timur Kristóf <[email protected]>
Acked-by: Christian König <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/si.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c > index 9d769222784c..f7288372ee61 100644 > --- a/drivers/gpu/drm/amd/amdgpu/si.c > +++ b/drivers/gpu/drm/amd/amdgpu/si.c > @@ -1918,6 +1918,14 @@ static int si_set_vce_clocks(struct amdgpu_device > *adev, u32 evclk, u32 ecclk) > ~VCEPLL_BYPASS_EN_MASK); > > if (!evclk || !ecclk) { > + /* > + * On some chips, the PLL takes way too long to get out of > + * sleep mode, causing a timeout waiting on CTLACK/CTLACK2. > + * Leave the PLL running in bypass mode. > + */ > + if (adev->pdev->device == 0x6780) > + return 0; > + > /* Keep the Bypass mode, put PLL to sleep */ > WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK, > ~VCEPLL_SLEEP_MASK);
