Move to emit_clk_levels from print_clk_levels
Signed-off-by: Lijo Lazar <[email protected]>
---
.../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 52 +++++++++----------
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
index eaa9ea162f16..45c0afb47c51 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
@@ -491,11 +491,12 @@ static int
renoir_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
return 0;
}
-static int renoir_print_clk_levels(struct smu_context *smu,
- enum smu_clk_type clk_type, char *buf)
+static int renoir_emit_clk_levels(struct smu_context *smu,
+ enum smu_clk_type clk_type, char *buf,
+ int *offset)
{
- int i, idx, size = 0, ret = 0, start_offset = 0;
uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
+ int i, idx, size = *offset, ret = 0, start_offset = *offset;
SmuMetrics_t metrics;
bool cur_value_match_level = false;
@@ -505,9 +506,6 @@ static int renoir_print_clk_levels(struct smu_context *smu,
if (ret)
return ret;
- smu_cmn_get_sysfs_buf(&buf, &size);
- start_offset = size;
-
switch (clk_type) {
case SMU_OD_RANGE:
ret = smu_cmn_send_smc_msg_with_param(smu,
@@ -534,24 +532,24 @@ static int renoir_print_clk_levels(struct smu_context
*smu,
/* retirve table returned paramters unit is MHz */
cur_value = metrics.ClockFrequency[CLOCK_GFXCLK];
ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max);
- if (!ret) {
- /* driver only know min/max gfx_clk, Add level 1 for
all other gfx clks */
- if (cur_value == max)
- i = 2;
- else if (cur_value == min)
- i = 0;
- else
- i = 1;
-
- size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
- i == 0 ? "*" : "");
- size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
- i == 1 ? cur_value :
RENOIR_UMD_PSTATE_GFXCLK,
- i == 1 ? "*" : "");
- size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
- i == 2 ? "*" : "");
- }
- return size - start_offset;
+ if (ret)
+ return ret;
+ /* driver only know min/max gfx_clk, Add level 1 for all other
gfx clks */
+ if (cur_value == max)
+ i = 2;
+ else if (cur_value == min)
+ i = 0;
+ else
+ i = 1;
+ size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
+ i == 0 ? "*" : "");
+ size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
+ i == 1 ? cur_value :
+ RENOIR_UMD_PSTATE_GFXCLK,
+ i == 1 ? "*" : "");
+ size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
+ i == 2 ? "*" : "");
+ break;
case SMU_SOCCLK:
count = NUM_SOCCLK_DPM_LEVELS;
cur_value = metrics.ClockFrequency[CLOCK_SOCCLK];
@@ -608,7 +606,9 @@ static int renoir_print_clk_levels(struct smu_context *smu,
break;
}
- return size - start_offset;
+ *offset += size - start_offset;
+
+ return 0;
}
static enum amd_pm_state_type renoir_get_current_power_state(struct
smu_context *smu)
@@ -1450,7 +1450,7 @@ static int renoir_get_enabled_mask(struct smu_context
*smu,
static const struct pptable_funcs renoir_ppt_funcs = {
.set_power_state = NULL,
- .print_clk_levels = renoir_print_clk_levels,
+ .emit_clk_levels = renoir_emit_clk_levels,
.get_current_power_state = renoir_get_current_power_state,
.dpm_set_vcn_enable = renoir_dpm_set_vcn_enable,
.dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable,
--
2.49.0
