Re: [PATCH] drm/amd/pm: fix issue of missing '*' on pp_dpm_xxx nodes

[Lazar, Lijo]

On 12-Jan-26 3:42 PM, Yang Wang wrote:
refine the code to fix '*' missing on pp_dpm_xxx series node.

e.g.: missing '*' on navi10 pp_dpm_sclk
$ cat /sys/class/drm/card0/device/pp_dpm_sclk
0: 300Mhz
1: 1930Mhz (the symbol of '*' is missing)

Fixes: d259c895d622 ("drm/amd/pm: Add a helper to show dpm table")

This fix doesn't look related. Could you also add the sample values 
under which the existing logic fails?

Thanks,
Lijo


Signed-off-by: Yang Wang <kevinyang.w...@amd.com>
---
  drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 31 +++++++++++++-------------
  1 file changed, 16 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index e0a508653b6a..60fc730bf81d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -1210,11 +1210,11 @@ int smu_cmn_print_dpm_clk_levels(struct smu_context 
*smu,
                                 struct smu_dpm_table *dpm_table,
                                 uint32_t cur_clk, char *buf, int *offset)
  {
-       uint32_t min_clk, level_index, count;
-       uint32_t freq_values[3] = { 0 };
+       uint32_t min_clk, max_clk, level_index, count;
+       uint32_t freq_values[3];
+       int size, lvl, i;
        bool is_fine_grained;
        bool is_deep_sleep;
-       int size, lvl, i;
        bool freq_match;
  
  	if (!dpm_table || !buf)
@@ -1225,6 +1225,7 @@ int smu_cmn_print_dpm_clk_levels(struct smu_context *smu,
        count = dpm_table->count;
        is_fine_grained = dpm_table->flags & SMU_DPM_TABLE_FINE_GRAINED;
        min_clk = SMU_DPM_TABLE_MIN(dpm_table);
+       max_clk = SMU_DPM_TABLE_MAX(dpm_table);
  
  	/* Deep sleep - current clock < min_clock/2, TBD: cur_clk = 0 as GFXOFF */
        is_deep_sleep = cur_clk < min_clk / 2;
@@ -1245,22 +1246,22 @@ int smu_cmn_print_dpm_clk_levels(struct smu_context 
*smu,
                                              freq_match ? "*" : "");
                }
        } else {
+               count = 2;
                freq_values[0] = min_clk;
-               freq_values[2] = SMU_DPM_TABLE_MAX(dpm_table);
-               freq_values[1] = cur_clk;
+               freq_values[1] = max_clk;
  
-		lvl = -1;
                if (!is_deep_sleep) {
-                       lvl = 1;
-                       if (smu_cmn_freqs_match(cur_clk, freq_values[0]))
+                       if (smu_cmn_freqs_match(cur_clk, min_clk)) {
                                lvl = 0;
-                       else if (smu_cmn_freqs_match(cur_clk, freq_values[2]))
-                               lvl = 2;
-               }
-               count = 3;
-               if (lvl != 1) {
-                       count = 2;
-                       freq_values[1] = freq_values[2];
+                       } else if (smu_cmn_freqs_match(cur_clk, max_clk)) {
+                               lvl = 1;
+                       } else {
+                               /* NOTE: use index '1' to show current clock 
value */
+                               lvl = 1;
+                               count = 3;
+                               freq_values[1] = cur_clk;
+                               freq_values[2] = max_clk;
+                       }
                }
  
  		for (i = 0; i < count; i++) {