Pass the seq as a parameter. No intended functional change. This paves the way for future improvements to queue reset handling by making the sync point explicit rather then implicit.
Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/si_dma.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 8 ++++---- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 4 ++-- 25 files changed, 63 insertions(+), 50 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index ce095427611fb..da437c349aab9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -252,7 +252,7 @@ struct amdgpu_ring_funcs { uint32_t flags); void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, uint64_t seq, unsigned flags); - void (*emit_pipeline_sync)(struct amdgpu_ring *ring); + void (*emit_pipeline_sync)(struct amdgpu_ring *ring, u32 seq); void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid, uint64_t pd_addr); void (*emit_hdp_flush)(struct amdgpu_ring *ring); @@ -436,7 +436,7 @@ struct amdgpu_ring { #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) #define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags))) -#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) +#define amdgpu_ring_emit_pipeline_sync(r, s) (r)->funcs->emit_pipeline_sync((r), (s)) #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 0eccb31793ca7..c05a9f80053d4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -820,7 +820,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, ring->cond_exe_gpu_addr); if (need_pipe_sync) - amdgpu_ring_emit_pipeline_sync(ring); + amdgpu_ring_emit_pipeline_sync(ring, ring->fence_drv.sync_seq); if (cleaner_shader_needed) ring->funcs->emit_cleaner_shader(ring); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c index 9fb1946be1ba2..54ee78c034cdb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c @@ -564,9 +564,9 @@ static void vpe_ring_emit_fence(struct amdgpu_ring *ring, uint64_t addr, } -static void vpe_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +static void vpe_ring_emit_pipeline_sync(struct amdgpu_ring *ring, + u32 seq) { - uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; vpe_ring_emit_pred_exec(ring, 0, 6); diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index e2ca96f5a7cfb..21b3a815bf2a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -821,12 +821,13 @@ static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) * cik_sdma_ring_emit_pipeline_sync - sync the pipeline * * @ring: amdgpu_ring pointer + * @seq: seq number to wait on * * Make sure all previous operations are completed (CIK). */ -static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring, + u32 seq) { - uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; /* wait for idle */ diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 496121bdc1de1..e0e125eef9ac5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -8736,10 +8736,10 @@ static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, amdgpu_ring_write(ring, 0); } -static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring, + u32 seq) { int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); - uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 5ad2516a60240..cc9ac87c5be02 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -5966,10 +5966,10 @@ static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, amdgpu_ring_write(ring, 0); } -static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring, + u32 seq) { int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); - uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 5862b5f60a6ee..cbe175145286b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -4483,10 +4483,10 @@ static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, amdgpu_ring_write(ring, 0); } -static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring, + u32 seq) { int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); - uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 7d02569cd4738..b7e1d7546267c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -3381,10 +3381,10 @@ static void gfx_v12_1_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, amdgpu_ring_write(ring, 0); } -static void gfx_v12_1_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +static void gfx_v12_1_ring_emit_pipeline_sync(struct amdgpu_ring *ring, + u32 seq) { int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); - uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; gfx_v12_1_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 2f8aa99f17480..fcc1e75146e90 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -2287,10 +2287,10 @@ static int gfx_v6_0_cp_resume(struct amdgpu_device *adev) return 0; } -static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring, + u32 seq) { int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); - uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index fa235b981c2e9..4ffff8ad4dc83 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -3096,14 +3096,15 @@ static int gfx_v7_0_cp_resume(struct amdgpu_device *adev) * gfx_v7_0_ring_emit_pipeline_sync - cik vm flush using the CP * * @ring: the ring to emit the commands to + * @seq: sequence number to wait for * * Sync the command pipeline with the PFP. E.g. wait for everything * to be completed. */ -static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring, + u32 seq) { int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); - uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 4736216cd0211..f88cfef175c0f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -6176,10 +6176,10 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, } -static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring, + u32 seq) { int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); - uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 36f0300a21bfa..07fe959abe0d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -5606,7 +5606,8 @@ static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring *ring) amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ } -static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring, + u32 seq) { if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { gfx_v9_0_ring_emit_event_write(ring, VS_PARTIAL_FLUSH, 4); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index d78b2c2ae13a3..fb731e877c99c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2904,10 +2904,10 @@ static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, amdgpu_ring_write(ring, 0); } -static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring, + u32 seq) { int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); - uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 46263d50cc9ef..42dca080e1dd5 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -756,12 +756,13 @@ static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline * * @ring: amdgpu_ring pointer + * @seq: seq number to wait on * * Make sure all previous operations are completed (CIK). */ -static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring, + u32 seq) { - uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; /* wait for idle */ diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index f9f05768072ad..b6e0d035c27eb 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -1029,12 +1029,13 @@ static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline * * @ring: amdgpu_ring pointer + * @seq: seq number to wait on * * Make sure all previous operations are completed (CIK). */ -static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring, + u32 seq) { - uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; /* wait for idle */ diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 56d2832ccba2d..ae6b9f344e20d 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -1691,12 +1691,13 @@ static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline * * @ring: amdgpu_ring pointer + * @seq: seq number to wait on * * Make sure all previous operations are completed (CIK). */ -static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring, + u32 seq) { - uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; /* wait for idle */ diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index dd8d6a572710d..86b800e2b4329 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -1287,12 +1287,13 @@ static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib * * sdma_v4_4_2_ring_emit_pipeline_sync - sync the pipeline * * @ring: amdgpu_ring pointer + * @seq: seq number to wait on * * Make sure all previous operations are completed (CIK). */ -static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring, + u32 seq) { - uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; /* wait for idle */ diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index 786f1776fa30d..c5dc727c7b448 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -1259,12 +1259,13 @@ static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline * * @ring: amdgpu_ring pointer + * @seq: seq number to wait on * * Make sure all previous operations are completed (CIK). */ -static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring, + u32 seq) { - uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; /* wait for idle */ diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 49005b96aa3f2..3076734462d25 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -1160,12 +1160,13 @@ static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline * * @ring: amdgpu_ring pointer + * @seq: seq number to wait on * * Make sure all previous operations are completed (CIK). */ -static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring, + u32 seq) { - uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; /* wait for idle */ diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 210ea6ba6212f..fbac29485d0c8 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -1165,12 +1165,13 @@ static void sdma_v6_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib * sdma_v6_0_ring_emit_pipeline_sync - sync the pipeline * * @ring: amdgpu_ring pointer + * @seq: seq number to wait on * * Make sure all previous operations are completed (CIK). */ -static void sdma_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +static void sdma_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring, + u32 seq) { - uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; /* wait for idle */ diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index 3b4417d19212e..bb9fae2c8dee0 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -1185,12 +1185,13 @@ static void sdma_v7_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib * sdma_v7_0_ring_emit_pipeline_sync - sync the pipeline * * @ring: amdgpu_ring pointer + * @seq: seq number to wait on * * Make sure all previous operations are completed (CIK). */ -static void sdma_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +static void sdma_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring, + u32 seq) { - uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; /* wait for idle */ diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c index d71a546bdde61..5efdb4dcbed97 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c @@ -1182,12 +1182,13 @@ static void sdma_v7_1_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib * sdma_v7_1_ring_emit_pipeline_sync - sync the pipeline * * @ring: amdgpu_ring pointer + * @seq: seq number to wait on * * Make sure all previous operations are completed (CIK). */ -static void sdma_v7_1_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +static void sdma_v7_1_ring_emit_pipeline_sync(struct amdgpu_ring *ring, + u32 seq) { - uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; /* wait for idle */ diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index b67bd343f795f..3f5fe58c47165 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -428,12 +428,13 @@ static void si_dma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) * si_dma_ring_emit_pipeline_sync - sync the pipeline * * @ring: amdgpu_ring pointer + * @seq: seq number to wait on * * Make sure all previous operations are completed (CIK). */ -static void si_dma_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +static void si_dma_ring_emit_pipeline_sync(struct amdgpu_ring *ring, + u32 seq) { - uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; /* wait for idle */ diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index ecd7ead7a60b1..ef9a822ec6701 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -1089,9 +1089,9 @@ static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, amdgpu_ring_write(ring, 0xC); } -static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring, + u32 seq) { - uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); @@ -1118,9 +1118,9 @@ static void uvd_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) } } -static void uvd_v6_0_enc_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +static void uvd_v6_0_enc_ring_emit_pipeline_sync(struct amdgpu_ring *ring, + u32 seq) { - uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; amdgpu_ring_write(ring, HEVC_ENC_CMD_WAIT_GE); diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index 03d79e464f04f..4a6f16c8e9c1b 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -887,9 +887,9 @@ static void vce_v3_0_emit_vm_flush(struct amdgpu_ring *ring, amdgpu_ring_write(ring, VCE_CMD_END); } -static void vce_v3_0_emit_pipeline_sync(struct amdgpu_ring *ring) +static void vce_v3_0_emit_pipeline_sync(struct amdgpu_ring *ring, + u32 seq) { - uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; amdgpu_ring_write(ring, VCE_CMD_WAIT_GE); -- 2.52.0
