Resetting VCN resets the entire tile, including JPEG hardware.
When we reset VCN, we need to ensure the JPEG block is accessible
for proper reset handling and queue recovery.

Signed-off-by: Jesse Zhang <[email protected]>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 26 ++++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
index db2c8efb112c..c28c6aff17aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
@@ -1362,10 +1362,19 @@ static int vcn_v5_0_1_ring_reset(struct amdgpu_ring 
*ring,
        int vcn_inst;
        struct amdgpu_device *adev = ring->adev;
        struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me];
+       bool pg_state = false;
 
        /* take the vcn reset mutex here because resetting VCN will reset jpeg 
as well */
        mutex_lock(&vinst->engine_reset_mutex);
        vcn_v5_0_1_reset_jpeg_pre_helper(adev, ring->me);
+       mutex_lock(&adev->jpeg.jpeg_pg_lock);
+       /* Ensure JPEG is powered on during reset if currently gated */
+       if (adev->jpeg.cur_state == AMD_PG_STATE_GATE) {
+               amdgpu_device_ip_set_powergating_state(adev, 
AMD_IP_BLOCK_TYPE_JPEG,
+                                              AMD_PG_STATE_UNGATE);
+               pg_state = true;
+       }
+
        amdgpu_ring_reset_helper_begin(ring, timedout_fence);
 
        vcn_inst = GET_INST(VCN, ring->me);
@@ -1373,6 +1382,11 @@ static int vcn_v5_0_1_ring_reset(struct amdgpu_ring 
*ring,
 
        if (r) {
                DRM_DEV_ERROR(adev->dev, "VCN reset fail : %d\n", r);
+               /* Restore JPEG power gating state if it was originally gated */
+               if (pg_state)
+                       amdgpu_device_ip_set_powergating_state(adev, 
AMD_IP_BLOCK_TYPE_JPEG,
+                                                              
AMD_PG_STATE_GATE);
+               mutex_unlock(&adev->jpeg.jpeg_pg_lock);
                goto unlock;
        }
 
@@ -1380,8 +1394,18 @@ static int vcn_v5_0_1_ring_reset(struct amdgpu_ring 
*ring,
        vcn_v5_0_1_start_dpg_mode(vinst, vinst->indirect_sram);
 
        r = amdgpu_ring_reset_helper_end(ring, timedout_fence);
-       if (r)
+       if (r) {
+               if (pg_state)
+                       amdgpu_device_ip_set_powergating_state(adev, 
AMD_IP_BLOCK_TYPE_JPEG,
+                                                              
AMD_PG_STATE_GATE);
+               mutex_unlock(&adev->jpeg.jpeg_pg_lock);
                goto unlock;
+       }
+
+       if (pg_state)
+               amdgpu_device_ip_set_powergating_state(adev, 
AMD_IP_BLOCK_TYPE_JPEG,
+                                                      AMD_PG_STATE_GATE);
+       mutex_unlock(&adev->jpeg.jpeg_pg_lock);
 
        r = vcn_v5_0_1_reset_jpeg_post_helper(adev, ring->me);
 
-- 
2.49.0

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