From: Bhuvanachandra Pinninti <[email protected]> [why] Direct HUBBUB register access in the hwseq layer was creating register conflicts.
[how] Migrated HUBBUB registers from hwseq to the hubbub component. Reviewed-by: Martin Leung <[email protected]> Signed-off-by: Bhuvanachandra Pinninti <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> --- .../amd/display/dc/hubbub/dcn10/dcn10_hubbub.c | 18 ++++++++++++++++++ .../amd/display/dc/hubbub/dcn10/dcn10_hubbub.h | 4 ++++ .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 3 +-- .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 4 ++-- .../amd/display/dc/hwss/dcn201/dcn201_hwseq.c | 1 + .../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 1 + .../amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 1 + .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 1 + 8 files changed, 29 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c index 7847c1c4927b..97ef8281a476 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c @@ -944,3 +944,21 @@ void hubbub1_construct(struct hubbub *hubbub, hubbub1->debug_test_index_pstate = 0xB; } +void dcn10_hubbub_global_timer_enable(struct hubbub *hubbub, bool enable, uint32_t refdiv) +{ + struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); + + if (refdiv > 0) + REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, refdiv); + + REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, enable ? 1 : 0); +} + +void dcn10_hubbub_read_fb_aperture(struct hubbub *hubbub, uint32_t *fb_base_value, uint32_t *fb_offset_value) +{ + struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); + + REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, fb_base_value); + REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, fb_offset_value); +} + diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h index 0a29a758d013..990d3cd8e050 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h @@ -519,4 +519,8 @@ bool hubbub1_program_pstate_watermarks( unsigned int refclk_mhz, bool safe_to_lower); +void dcn10_hubbub_global_timer_enable(struct hubbub *hubbub, bool enable, uint32_t refdiv); + +void dcn10_hubbub_read_fb_aperture(struct hubbub *hubbub, uint32_t *fb_base_value, uint32_t *fb_offset_value); + #endif diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 73f469ce7cdd..c1586364ecd4 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -2678,8 +2678,7 @@ static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1, uint32_t fb_base_value; uint32_t fb_offset_value; - REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value); - REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value); + dcn10_hubbub_read_fb_aperture(hws->ctx->dc->res_pool->hubbub, &fb_base_value, &fb_offset_value); REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 16ea6179640e..a76436dcbe40 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -46,6 +46,7 @@ #include "dchubbub.h" #include "reg_helper.h" #include "dcn10/dcn10_cm_common.h" +#include "dcn10/dcn10_hubbub.h" #include "vm_helper.h" #include "dccg.h" #include "dc_dmub_srv.h" @@ -3153,8 +3154,7 @@ void dcn20_fpga_init_hw(struct dc *dc) REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); - REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); - REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); + dcn10_hubbub_global_timer_enable(dc->res_pool->hubbub, true, 2); if (REG(REFCLK_CNTL)) REG_WRITE(REFCLK_CNTL, 0); // diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c index 1635e5a552ad..482053c4ad22 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c @@ -39,6 +39,7 @@ #include "dccg.h" #include "clk_mgr.h" #include "reg_helper.h" +#include "dcn10/dcn10_hubbub.h" #define CTX \ hws->ctx diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c index 81bcadf5e57e..c02ddada723f 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c @@ -36,6 +36,7 @@ #include "dcn10/dcn10_cm_common.h" #include "dcn30/dcn30_cm_common.h" #include "reg_helper.h" +#include "dcn10/dcn10_hubbub.h" #include "abm.h" #include "clk_mgr.h" #include "hubp.h" diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index 20f700b59847..2adbcc105aa6 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -32,6 +32,7 @@ #include "dce/dce_hwseq.h" #include "clk_mgr.h" #include "reg_helper.h" +#include "dcn10/dcn10_hubbub.h" #include "abm.h" #include "hubp.h" #include "dchubbub.h" diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index 2675d7dca586..f7e16fee7594 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -32,6 +32,7 @@ #include "dce/dce_hwseq.h" #include "clk_mgr.h" #include "reg_helper.h" +#include "dcn10/dcn10_hubbub.h" #include "abm.h" #include "hubp.h" #include "dchubbub.h" -- 2.52.0
