MES FW uses addr(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t)) as fence address and writes a 32 bit fence value to this address.
Driver needs to allocate some extra memory(at least 4 DWs) in addition to sizeof(struct mqd) as mqd memory. For gfx11/12, sizeof(struct mqd) < PAGE_SIZE, allocate mqd memory with PAGE_SIZE aligned works. For gfx12.1, sizeof(struct mqd) == PAGE_SIZE, it doesn't work. KFD mqd manager hardcodes mqd size to PAGE_SIZE/MQD_SIZE. Let's use AMDGPU_MQD_SIZE_ALIGN to avoid hardcoding in differnet place and across different IP version. It is used in two place. 1. mqd memory alloction 2. mqd stride initialization Signed-off-by: Lang Yu <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 9c11535c44c6..41f32ed39113 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1239,6 +1239,11 @@ struct amdgpu_device { struct amdgpu_kfd_dev kfd; }; +/* + * MES will use memory beyond struct MQD size, 5 DWs currently + */ +#define AMDGPU_MQD_SIZE_ALIGN(mqd_size) ALIGN(((mqd_size) + 20), PAGE_SIZE) + static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, uint8_t ip, uint8_t inst) { -- 2.34.1
