Combine PTL hardware control with the existing PMC device locking mechanism to ensure proper synchronization and hardware state management during profiling operations.
Signed-off-by: Perry Yuan <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Acked-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index dbb111a33678..1e619eda8433 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1764,6 +1764,27 @@ static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) } #endif +static int kfd_ptl_control(struct kfd_process_device *pdd, bool enable) +{ + struct amdgpu_device *adev = pdd->dev->adev; + enum amdgpu_ptl_fmt pref_format1 = adev->psp.ptl_fmt1; + enum amdgpu_ptl_fmt pref_format2 = adev->psp.ptl_fmt2; + uint32_t ptl_state = enable ? 1 : 0; + int ret; + + if (!adev->psp.ptl_hw_supported) + return -EOPNOTSUPP; + + if (!pdd->dev->kfd2kgd || !pdd->dev->kfd2kgd->ptl_ctrl) + return -EOPNOTSUPP; + + ret = pdd->dev->kfd2kgd->ptl_ctrl(adev, PSP_PTL_PERF_MON_SET, + &ptl_state, + &pref_format1, + &pref_format2); + return ret; +} + static int criu_checkpoint_process(struct kfd_process *p, uint8_t __user *user_priv_data, uint64_t *priv_offset) @@ -3229,6 +3250,7 @@ static inline uint32_t profile_lock_device(struct kfd_process *p, if (!kfd->profiler_process) { kfd->profiler_process = p; status = 0; + kfd_ptl_control(pdd, false); } else if (kfd->profiler_process == p) { status = -EALREADY; } else { @@ -3237,6 +3259,7 @@ static inline uint32_t profile_lock_device(struct kfd_process *p, } else if (op == 0 && kfd->profiler_process == p) { kfd->profiler_process = NULL; status = 0; + kfd_ptl_control(pdd, true); } mutex_unlock(&kfd->profiler_lock); -- 2.34.1
