[AMD Official Use Only - AMD Internal Distribution Only] Series is
Reviewed-by: Asad Kamal <[email protected]> Thanks & Regards Asad -----Original Message----- From: Lazar, Lijo <[email protected]> Sent: Tuesday, February 10, 2026 12:04 PM To: [email protected] Cc: Zhang, Hawking <[email protected]>; Deucher, Alexander <[email protected]>; Kamal, Asad <[email protected]> Subject: [PATCH 1/2] drm/amdgpu: Remove amdgpu_device_flush_hdp Merge the logic into amdgpu_hdp_flush and use it as the public interface. Signed-off-by: Lijo Lazar <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 -- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 25 +------------------ drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 6 ++--- drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c | 17 +++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 12 ++++----- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 6 ++--- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/psp_v14_0.c | 2 +- .../drm/amd/amdkfd/kfd_device_queue_manager.c | 2 +- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 6 ++--- 23 files changed, 55 insertions(+), 63 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 1f5d15110e43..c1eded4bfa75 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1527,8 +1527,6 @@ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, int amdgpu_device_baco_enter(struct amdgpu_device *adev); int amdgpu_device_baco_exit(struct amdgpu_device *adev); -void amdgpu_device_flush_hdp(struct amdgpu_device *adev, - struct amdgpu_ring *ring); void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 3bfd79c89df3..ed153e9008e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -738,7 +738,7 @@ bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev) void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev) { - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); } bool amdgpu_amdkfd_is_fed(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 48540300b10a..212eadb90c6c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -771,7 +771,7 @@ size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, * after the system memory contents are sent over PCIe device */ mb(); - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); } else { amdgpu_device_invalidate_hdp(adev, NULL); /* Make sure HDP read cache is invalidated before issuing a read @@ -7288,29 +7288,6 @@ bool amdgpu_device_load_pci_state(struct pci_dev *pdev) return true; } -void amdgpu_device_flush_hdp(struct amdgpu_device *adev, - struct amdgpu_ring *ring) -{ -#ifdef CONFIG_X86_64 - if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) - return; -#endif - if (adev->gmc.xgmi.connected_to_cpu) - return; - - if (ring && ring->funcs->emit_hdp_flush) { - amdgpu_ring_emit_hdp_flush(ring); - return; - } - - if (!ring && amdgpu_sriov_runtime(adev)) { - if (!amdgpu_kiq_hdp_flush(adev)) - return; - } - - amdgpu_hdp_flush(adev, ring); -} - void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c index ec911dce345f..0f4a39f48c36 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c @@ -443,7 +443,7 @@ void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev) mb(); if (down_read_trylock(&adev->reset_domain->sem)) { - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); up_read(&adev->reset_domain->sem); } for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index cab3196a87fb..eeec7947fc49 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -676,7 +676,7 @@ static int amdgpu_gfx_mes_enable_kcq(struct amdgpu_device *adev, int xcc_id) uint64_t queue_mask = ~0ULL; int r, i, j; - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); if (!adev->enable_uni_mes) { spin_lock(&kiq->ring_lock); @@ -736,7 +736,7 @@ int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id) queue_mask |= (1ull << amdgpu_queue_mask_bit_to_set_resource_bit(adev, i)); } - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); dev_info(adev->dev, "kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe, kiq_ring->queue); @@ -781,7 +781,7 @@ int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id) if (!kiq->pmf || !kiq->pmf->kiq_map_queues) return -EINVAL; - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); if (adev->mes.enable_legacy_queue_map) { for (i = 0; i < adev->gfx.num_gfx_rings; i++) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c index 5a60d69a3e1f..c085031a6f09 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c @@ -77,6 +77,23 @@ void amdgpu_hdp_invalidate(struct amdgpu_device *adev, struct amdgpu_ring *ring) void amdgpu_hdp_flush(struct amdgpu_device *adev, struct amdgpu_ring *ring) { +#ifdef CONFIG_X86_64 + if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) + return; +#endif + if (adev->gmc.xgmi.connected_to_cpu) + return; + + if (ring && ring->funcs->emit_hdp_flush) { + amdgpu_ring_emit_hdp_flush(ring); + return; + } + + if (!ring && amdgpu_sriov_runtime(adev)) { + if (!amdgpu_kiq_hdp_flush(adev)) + return; + } + if (adev->asic_funcs && adev->asic_funcs->flush_hdp) adev->asic_funcs->flush_hdp(adev, ring); else if (adev->hdp.funcs && adev->hdp.funcs->flush_hdp) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 44f230d67da2..f4885a140967 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -243,7 +243,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, cond_exec = amdgpu_ring_init_cond_exec(ring, ring->cond_exe_gpu_addr); - amdgpu_device_flush_hdp(adev, ring); + amdgpu_hdp_flush(adev, ring); if (need_ctx_switch) status |= AMDGPU_HAVE_CTX_SWITCH; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index b0540b009e84..57a8ac2c69db 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -3479,7 +3479,7 @@ int psp_ring_cmd_submit(struct psp_context *psp, write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); write_frame->fence_value = index; - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); /* Update the write Pointer in DWORDs */ psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c index 22e2e5b47341..df978a39ed96 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c @@ -112,7 +112,7 @@ static int amdgpu_vm_cpu_commit(struct amdgpu_vm_update_params *p, atomic64_inc(&p->vm->tlb_seq); mb(); - amdgpu_device_flush_hdp(p->adev, NULL); + amdgpu_hdp_flush(p->adev, NULL); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 1893ceeeb26c..b413f10e51c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -6153,7 +6153,7 @@ static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) } if (amdgpu_emu_mode == 1) - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); @@ -6231,7 +6231,7 @@ static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) } if (amdgpu_emu_mode == 1) - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); @@ -6308,7 +6308,7 @@ static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) } if (amdgpu_emu_mode == 1) - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); @@ -6683,7 +6683,7 @@ static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) } if (amdgpu_emu_mode == 1) - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index b1a1b8a10a08..f4eba3247533 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -2522,7 +2522,7 @@ static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr) } if (amdgpu_emu_mode == 1) - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); @@ -2566,7 +2566,7 @@ static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr) } if (amdgpu_emu_mode == 1) - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); @@ -2611,7 +2611,7 @@ static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr) } if (amdgpu_emu_mode == 1) - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); @@ -3248,7 +3248,7 @@ static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); if (amdgpu_emu_mode == 1) - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); @@ -3466,7 +3466,7 @@ static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); if (amdgpu_emu_mode == 1) - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); @@ -4703,7 +4703,7 @@ static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev) if (r) return r; - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index a418ae609c36..3d068dca1442 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -2405,7 +2405,7 @@ static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); if (amdgpu_emu_mode == 1) - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); @@ -2549,7 +2549,7 @@ static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); if (amdgpu_emu_mode == 1) - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); @@ -3560,7 +3560,7 @@ static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev) if (r) return r; - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index 2568eeaae945..dffb130489a2 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -250,7 +250,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; /* flush hdp cache */ - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); /* This is necessary for SRIOV as well as for GFXOFF to function * properly under bare metal @@ -946,7 +946,7 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) adev->hdp.funcs->init_registers(adev); /* Flush HDP after it is initialized */ - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 6349e239a367..c322b438d0e0 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -238,7 +238,7 @@ static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; /* flush hdp cache */ - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); /* This is necessary for SRIOV as well as for GFXOFF to function * properly under bare metal @@ -918,7 +918,7 @@ static int gmc_v11_0_gart_enable(struct amdgpu_device *adev) return r; /* Flush HDP after it is initialized */ - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index b9671fc39e2a..2e5c373a8289 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -309,7 +309,7 @@ static void gmc_v12_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, return; /* flush hdp cache */ - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); /* This is necessary for SRIOV as well as for GFXOFF to function * properly under bare metal @@ -969,7 +969,7 @@ static int gmc_v12_0_gart_enable(struct amdgpu_device *adev) return r; /* Flush HDP after it is initialized */ - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index e35ed0cc2ec6..47b989036de6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -2175,7 +2175,7 @@ static int gmc_v9_0_hw_init(struct amdgpu_ip_block *ip_block) adev->hdp.funcs->init_registers(adev); /* After HDP is initialized, flush HDP.*/ - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) value = false; diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c index 0bd83820dd20..21eef7f6afb8 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c @@ -495,7 +495,7 @@ static int jpeg_v4_0_start_sriov(struct amdgpu_device *adev) memcpy((void *)table_loc, &header, size); /* Perform HDP flush before writing to MMSCH registers */ - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); /* message MMSCH (in VCN[0]) to initialize this client * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 09ebb13ca5e8..ec50df3ea9d0 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -1212,7 +1212,7 @@ static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; - amdgpu_device_flush_hdp(ring->adev, NULL); + amdgpu_hdp_flush(ring->adev, NULL); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c index 9aa988982304..691b305f28c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c @@ -551,7 +551,7 @@ static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops) } memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); vfree(buf); drm_dev_exit(idx); } else { diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c index af4a7d7c4abd..7106ad806a9f 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c @@ -640,7 +640,7 @@ static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops) } memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); vfree(buf); drm_dev_exit(idx); } else { diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c index 38dfc5c19f2a..5fb35d9b0f5e 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c @@ -505,7 +505,7 @@ static int psp_v14_0_memory_training(struct psp_context *psp, uint32_t ops) } memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); - amdgpu_device_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); vfree(buf); drm_dev_exit(idx); } else { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 804851632c4c..da062d13414f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -3497,7 +3497,7 @@ int suspend_queues(struct kfd_process *p, dqm_unlock(dqm); mutex_unlock(&p->event_mutex); - amdgpu_device_flush_hdp(dqm->dev->adev, NULL); + amdgpu_hdp_flush(dqm->dev->adev, NULL); } if (total_suspended) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index dcf4bbfa641b..fbcb12e0888a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -754,7 +754,7 @@ static void init_mqd_v9_4_3(struct mqd_manager *mm, void **mqd, } if (mqd_on_vram(mm->dev->adev)) - amdgpu_device_flush_hdp(mm->dev->adev, NULL); + amdgpu_hdp_flush(mm->dev->adev, NULL); } static void update_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, @@ -793,7 +793,7 @@ static void update_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, } if (mqd_on_vram(mm->dev->adev)) - amdgpu_device_flush_hdp(mm->dev->adev, NULL); + amdgpu_hdp_flush(mm->dev->adev, NULL); } static void restore_mqd_v9_4_3(struct mqd_manager *mm, void **mqd, @@ -834,7 +834,7 @@ static void restore_mqd_v9_4_3(struct mqd_manager *mm, void **mqd, } if (mqd_on_vram(mm->dev->adev)) - amdgpu_device_flush_hdp(mm->dev->adev, NULL); + amdgpu_hdp_flush(mm->dev->adev, NULL); } static int destroy_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, enum kfd_preempt_type type, unsigned int timeout, -- 2.49.0
