From: Matthew Stewart <[email protected]> [Why & How] Add DMUB support for DCN42B
Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Matthew Stewart <[email protected]> Signed-off-by: Ray Wu <[email protected]> --- drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 + drivers/gpu/drm/amd/display/dmub/src/Makefile | 1 + .../drm/amd/display/dmub/src/dmub_dcn42b.c | 34 +++++++++++++++++++ .../drm/amd/display/dmub/src/dmub_dcn42b.h | 13 +++++++ .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 4 +++ 5 files changed, 53 insertions(+) create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42b.c create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42b.h diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h index c18ff8f00bb8..f4d05dcfef29 100644 --- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h @@ -121,6 +121,7 @@ enum dmub_asic { DMUB_ASIC_DCN36, DMUB_ASIC_DCN401, DMUB_ASIC_DCN42, + DMUB_ASIC_DCN42B, DMUB_ASIC_MAX, }; diff --git a/drivers/gpu/drm/amd/display/dmub/src/Makefile b/drivers/gpu/drm/amd/display/dmub/src/Makefile index ac7b17d8fb0f..b6f7477ada22 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/Makefile +++ b/drivers/gpu/drm/amd/display/dmub/src/Makefile @@ -29,6 +29,7 @@ DMUB += dmub_dcn351.o DMUB += dmub_dcn36.o DMUB += dmub_dcn401.o DMUB += dmub_dcn42.o +DMUB += dmub_dcn42b.o AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB)) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42b.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42b.c new file mode 100644 index 000000000000..97eb022b837b --- /dev/null +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42b.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + +#include "../dmub_srv.h" +#include "dmub_reg.h" +#include "dmub_dcn42b.h" + +#include "dcn/dcn_4_2_1_offset.h" +#include "dcn/dcn_4_2_1_sh_mask.h" + +#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] +#define CTX dmub +#define REGS dmub->regs_dcn42 +#define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name + +void dmub_srv_dcn42b_regs_init(struct dmub_srv *dmub, struct dc_context *ctx) +{ + struct dmub_srv_dcn42_regs *regs = dmub->regs_dcn42; +#define REG_STRUCT regs + +#define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg); + DMUB_DCN42_REGS() + DMCUB_INTERNAL_REGS() +#undef DMUB_SR + +#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field); + DMUB_DCN42_FIELDS() +#undef DMUB_SF + +#define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field); + DMUB_DCN42_FIELDS() +#undef DMUB_SF +#undef REG_STRUCT +} diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42b.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42b.h new file mode 100644 index 000000000000..cc89f177bf09 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42b.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + +#ifndef _DMUB_DCN42B_H_ +#define _DMUB_DCN42B_H_ + +#include "dmub_dcn42.h" + +struct dmub_srv; + +void dmub_srv_dcn42b_regs_init(struct dmub_srv *dmub, struct dc_context *ctx); + +#endif /* _DMUB_DCN42B_H_ */ diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c index 10d23f5f5d94..7463d2ae5055 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c @@ -41,6 +41,7 @@ #include "dmub_dcn36.h" #include "dmub_dcn401.h" #include "dmub_dcn42.h" +#include "dmub_dcn42b.h" #include "os_types.h" /* * Note: the DMUB service is standalone. No additional headers should be @@ -413,6 +414,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) funcs->should_detect = dmub_dcn35_should_detect; break; case DMUB_ASIC_DCN42: + case DMUB_ASIC_DCN42B: dmub->regs_dcn42 = &dmub_srv_dcn42_regs; funcs->configure_dmub_in_system_memory = dmub_dcn42_configure_dmub_in_system_memory; funcs->send_inbox0_cmd = dmub_dcn42_send_inbox0_cmd; @@ -466,6 +468,8 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) funcs->enable_reg_inbox0_rsp_int = dmub_dcn42_enable_reg_inbox0_rsp_int; funcs->enable_reg_outbox0_rdy_int = dmub_dcn42_enable_reg_outbox0_rdy_int; funcs->init_reg_offsets = dmub_srv_dcn42_regs_init; + if (asic == DMUB_ASIC_DCN42B) + funcs->init_reg_offsets = dmub_srv_dcn42b_regs_init; funcs->is_hw_powered_up = dmub_dcn42_is_hw_powered_up; funcs->should_detect = dmub_dcn42_should_detect; -- 2.43.0
