[PATCH 04/43] drm/amdgpu/gfx10: replace BUG_ON() with WARN_ON()

[Alex Deucher]

There's no need to crash the kernel for these cases.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index e99d17cd43e57..544d6aafb11a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4022,7 +4022,7 @@ static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring 
*ring, int eng_sel,
                           WAIT_REG_MEM_ENGINE(eng_sel)));
 
        if (mem_space)
-               BUG_ON(addr0 & 0x3); /* Dword align */
+               WARN_ON(addr0 & 0x3); /* Dword align */
        amdgpu_ring_write(ring, addr0);
        amdgpu_ring_write(ring, addr1);
        amdgpu_ring_write(ring, ref);
@@ -8661,7 +8661,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring 
*ring,
        }
 
        amdgpu_ring_write(ring, header);
-       BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
+       WARN_ON(ib->gpu_addr & 0x3); /* Dword align */
        amdgpu_ring_write(ring,
 #ifdef __BIG_ENDIAN
                (2 << 0) |
@@ -8696,7 +8696,7 @@ static void gfx_v10_0_ring_emit_ib_compute(struct 
amdgpu_ring *ring,
        }
 
        amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
-       BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
+       WARN_ON(ib->gpu_addr & 0x3); /* Dword align */
        amdgpu_ring_write(ring,
 #ifdef __BIG_ENDIAN
                                (2 << 0) |
@@ -8729,9 +8729,9 @@ static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring 
*ring, u64 addr,
         * aligned if only send 32bit data low (discard data high)
         */
        if (write64bit)
-               BUG_ON(addr & 0x7);
+               WARN_ON(addr & 0x7);
        else
-               BUG_ON(addr & 0x3);
+               WARN_ON(addr & 0x3);
        amdgpu_ring_write(ring, lower_32_bits(addr));
        amdgpu_ring_write(ring, upper_32_bits(addr));
        amdgpu_ring_write(ring, lower_32_bits(seq));
@@ -8779,9 +8779,6 @@ static void gfx_v10_0_ring_emit_fence_kiq(struct 
amdgpu_ring *ring, u64 addr,
 {
        struct amdgpu_device *adev = ring->adev;
 
-       /* we only allocate 32bit for each seq wb address */
-       BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
-
        /* write fence seq to the "addr" */
        amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
        amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-- 
2.54.0