On 6/17/26 21:14, Timur Kristóf wrote: > This was basically dead code, not used or called from anywhere. > > Now that DC is the default display driver for all ASICs, > it is unlikely that anyone wants to develop this further. > Display hang related work should be focused on DC. > > Signed-off-by: Timur Kristóf <[email protected]>
Reviewed-by: Christian König <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 66 -------------------------- > drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 57 ---------------------- > drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 57 ---------------------- > 3 files changed, 180 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c > index 055ec8196f90..20071c24edd5 100644 > --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c > @@ -410,36 +410,6 @@ static u32 dce_v10_0_hpd_get_gpio_reg(struct > amdgpu_device *adev) > return mmDC_GPIO_HPD_A; > } > > -static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev) > -{ > - u32 crtc_hung = 0; > - u32 crtc_status[6]; > - u32 i, j, tmp; > - > - for (i = 0; i < adev->mode_info.num_crtc; i++) { > - tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); > - if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { > - crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + > crtc_offsets[i]); > - crtc_hung |= (1 << i); > - } > - } > - > - for (j = 0; j < 10; j++) { > - for (i = 0; i < adev->mode_info.num_crtc; i++) { > - if (crtc_hung & (1 << i)) { > - tmp = RREG32(mmCRTC_STATUS_HV_COUNT + > crtc_offsets[i]); > - if (tmp != crtc_status[i]) > - crtc_hung &= ~(1 << i); > - } > - } > - if (crtc_hung == 0) > - return false; > - udelay(100); > - } > - > - return true; > -} > - > static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev, > bool render) > { > @@ -2956,40 +2926,6 @@ static bool dce_v10_0_is_idle(struct amdgpu_ip_block > *ip_block) > return true; > } > > -static bool dce_v10_0_check_soft_reset(struct amdgpu_ip_block *ip_block) > -{ > - struct amdgpu_device *adev = ip_block->adev; > - > - return dce_v10_0_is_display_hung(adev); > -} > - > -static int dce_v10_0_soft_reset(struct amdgpu_ip_block *ip_block) > -{ > - u32 srbm_soft_reset = 0, tmp; > - struct amdgpu_device *adev = ip_block->adev; > - > - if (dce_v10_0_is_display_hung(adev)) > - srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; > - > - if (srbm_soft_reset) { > - tmp = RREG32(mmSRBM_SOFT_RESET); > - tmp |= srbm_soft_reset; > - dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); > - WREG32(mmSRBM_SOFT_RESET, tmp); > - tmp = RREG32(mmSRBM_SOFT_RESET); > - > - udelay(50); > - > - tmp &= ~srbm_soft_reset; > - WREG32(mmSRBM_SOFT_RESET, tmp); > - tmp = RREG32(mmSRBM_SOFT_RESET); > - > - /* Wait a little for things to settle down */ > - udelay(50); > - } > - return 0; > -} > - > static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device > *adev, > int crtc, > enum > amdgpu_interrupt_state state) > @@ -3332,8 +3268,6 @@ static const struct amd_ip_funcs dce_v10_0_ip_funcs = { > .suspend = dce_v10_0_suspend, > .resume = dce_v10_0_resume, > .is_idle = dce_v10_0_is_idle, > - .check_soft_reset = dce_v10_0_check_soft_reset, > - .soft_reset = dce_v10_0_soft_reset, > .set_clockgating_state = dce_v10_0_set_clockgating_state, > .set_powergating_state = dce_v10_0_set_powergating_state, > }; > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c > b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c > index 0f47044bab5d..0eae0cca39ff 100644 > --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c > @@ -378,35 +378,6 @@ static u32 dce_v6_0_hpd_get_gpio_reg(struct > amdgpu_device *adev) > return mmDC_GPIO_HPD_A; > } > > -static bool dce_v6_0_is_display_hung(struct amdgpu_device *adev) > -{ > - u32 crtc_hung = 0; > - u32 crtc_status[6]; > - u32 i, j, tmp; > - > - for (i = 0; i < adev->mode_info.num_crtc; i++) { > - if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & > CRTC_CONTROL__CRTC_MASTER_EN_MASK) { > - crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + > crtc_offsets[i]); > - crtc_hung |= (1 << i); > - } > - } > - > - for (j = 0; j < 10; j++) { > - for (i = 0; i < adev->mode_info.num_crtc; i++) { > - if (crtc_hung & (1 << i)) { > - tmp = RREG32(mmCRTC_STATUS_HV_COUNT + > crtc_offsets[i]); > - if (tmp != crtc_status[i]) > - crtc_hung &= ~(1 << i); > - } > - } > - if (crtc_hung == 0) > - return false; > - udelay(100); > - } > - > - return true; > -} > - > static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev, > bool render) > { > @@ -2901,33 +2872,6 @@ static bool dce_v6_0_is_idle(struct amdgpu_ip_block > *ip_block) > return true; > } > > -static int dce_v6_0_soft_reset(struct amdgpu_ip_block *ip_block) > -{ > - u32 srbm_soft_reset = 0, tmp; > - struct amdgpu_device *adev = ip_block->adev; > - > - if (dce_v6_0_is_display_hung(adev)) > - srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; > - > - if (srbm_soft_reset) { > - tmp = RREG32(mmSRBM_SOFT_RESET); > - tmp |= srbm_soft_reset; > - dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); > - WREG32(mmSRBM_SOFT_RESET, tmp); > - tmp = RREG32(mmSRBM_SOFT_RESET); > - > - udelay(50); > - > - tmp &= ~srbm_soft_reset; > - WREG32(mmSRBM_SOFT_RESET, tmp); > - tmp = RREG32(mmSRBM_SOFT_RESET); > - > - /* Wait a little for things to settle down */ > - udelay(50); > - } > - return 0; > -} > - > static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device > *adev, > int crtc, > enum > amdgpu_interrupt_state state) > @@ -3224,7 +3168,6 @@ static const struct amd_ip_funcs dce_v6_0_ip_funcs = { > .suspend = dce_v6_0_suspend, > .resume = dce_v6_0_resume, > .is_idle = dce_v6_0_is_idle, > - .soft_reset = dce_v6_0_soft_reset, > .set_clockgating_state = dce_v6_0_set_clockgating_state, > .set_powergating_state = dce_v6_0_set_powergating_state, > }; > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c > b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c > index a885e8d47f70..c02b1345d9c2 100644 > --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c > @@ -362,35 +362,6 @@ static u32 dce_v8_0_hpd_get_gpio_reg(struct > amdgpu_device *adev) > return mmDC_GPIO_HPD_A; > } > > -static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev) > -{ > - u32 crtc_hung = 0; > - u32 crtc_status[6]; > - u32 i, j, tmp; > - > - for (i = 0; i < adev->mode_info.num_crtc; i++) { > - if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & > CRTC_CONTROL__CRTC_MASTER_EN_MASK) { > - crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + > crtc_offsets[i]); > - crtc_hung |= (1 << i); > - } > - } > - > - for (j = 0; j < 10; j++) { > - for (i = 0; i < adev->mode_info.num_crtc; i++) { > - if (crtc_hung & (1 << i)) { > - tmp = RREG32(mmCRTC_STATUS_HV_COUNT + > crtc_offsets[i]); > - if (tmp != crtc_status[i]) > - crtc_hung &= ~(1 << i); > - } > - } > - if (crtc_hung == 0) > - return false; > - udelay(100); > - } > - > - return true; > -} > - > static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev, > bool render) > { > @@ -2873,33 +2844,6 @@ static bool dce_v8_0_is_idle(struct amdgpu_ip_block > *ip_block) > return true; > } > > -static int dce_v8_0_soft_reset(struct amdgpu_ip_block *ip_block) > -{ > - u32 srbm_soft_reset = 0, tmp; > - struct amdgpu_device *adev = ip_block->adev; > - > - if (dce_v8_0_is_display_hung(adev)) > - srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; > - > - if (srbm_soft_reset) { > - tmp = RREG32(mmSRBM_SOFT_RESET); > - tmp |= srbm_soft_reset; > - dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); > - WREG32(mmSRBM_SOFT_RESET, tmp); > - tmp = RREG32(mmSRBM_SOFT_RESET); > - > - udelay(50); > - > - tmp &= ~srbm_soft_reset; > - WREG32(mmSRBM_SOFT_RESET, tmp); > - tmp = RREG32(mmSRBM_SOFT_RESET); > - > - /* Wait a little for things to settle down */ > - udelay(50); > - } > - return 0; > -} > - > static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device > *adev, > int crtc, > enum > amdgpu_interrupt_state state) > @@ -3241,7 +3185,6 @@ static const struct amd_ip_funcs dce_v8_0_ip_funcs = { > .suspend = dce_v8_0_suspend, > .resume = dce_v8_0_resume, > .is_idle = dce_v8_0_is_idle, > - .soft_reset = dce_v8_0_soft_reset, > .set_clockgating_state = dce_v8_0_set_clockgating_state, > .set_powergating_state = dce_v8_0_set_powergating_state, > };
