From: Karen Chen <[email protected]> [Why & How] DPP clock is gated when programming the cursor. This change disables DPPCLK RCG in dccg42_init before accessing DPP, ensuring cursor programming latches correctly.
Assisted-by: Cursor Reviewed-by: Ovidiu (Ovi) Bunea <[email protected]> Signed-off-by: Karen Chen <[email protected]> Signed-off-by: George Zhang <[email protected]> --- drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c index 8989761c6078..6cbc1f4ef411 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c @@ -292,6 +292,12 @@ static void dccg42_init(struct dccg *dccg) dccg42_disable_hdmistreamclk(dccg); if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar) dccg42_disable_hdmicharclk(dccg, 0); + + if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp) { + for (i = 0; i < res_pool->pipe_count; i++) { + dccg35_dpp_root_clock_control(dccg, i, true); + } + } } -- 2.54.0
