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On Thu, Jun 18, 2026 at 5:04 PM Alex Deucher <[email protected]> wrote: > > Add support for dumping IP register state. > > Signed-off-by: Alex Deucher <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 275 +++++++++++++++++++++++++ > 1 file changed, 275 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c > index 5bdf2512f1540..ec4346a6c2af2 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c > @@ -69,6 +69,127 @@ MODULE_FIRMWARE("amdgpu/gc_12_1_0_rlc_1.bin"); > (SH_MEM_ALIGNMENT_MODE_UNALIGNED_GFX12_1_0 << > SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ > (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) > > + > +static const struct amdgpu_hwip_reg_entry gc_reg_list_12_1[] = { > + SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), > + SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), > + SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), > + SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), > + SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), > + SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), > + SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), > + SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), > + SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), > + SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), > + SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), > + SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), > + SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), > + SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2), > + SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32), > + SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR), > + /* cp header registers */ > + SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), > + /* SE status registers */ > + SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), > + SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), > +}; > + > +static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12_1[] = { > + /* compute registers */ > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS), > + /* cp header registers */ > + SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), > + SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), > +}; > + > static void gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device *adev, int > xcc_id); > static void gfx_v12_1_set_ring_funcs(struct amdgpu_device *adev); > static void gfx_v12_1_set_irq_funcs(struct amdgpu_device *adev); > @@ -1148,6 +1269,153 @@ static int > gfx_v12_1_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) > return 0; > } > > +static void gfx_v12_1_alloc_ip_dump(struct amdgpu_device *adev) > +{ > + uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_1); > + uint32_t *ptr, inst, num_xcc; > + > + num_xcc = NUM_XCC(adev->gfx.xcc_mask); > + > + ptr = kcalloc(reg_count * num_xcc, sizeof(uint32_t), GFP_KERNEL); > + if (!ptr) { > + DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); > + adev->gfx.ip_dump_core = NULL; > + } else { > + adev->gfx.ip_dump_core = ptr; > + } > + > + /* Allocate memory for compute queue registers for all the instances > */ > + reg_count = ARRAY_SIZE(gc_cp_reg_list_12_1); > + inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * > + adev->gfx.mec.num_queue_per_pipe; > + > + ptr = kcalloc(reg_count * inst * num_xcc, sizeof(uint32_t), > GFP_KERNEL); > + if (!ptr) { > + DRM_ERROR("Failed to allocate memory for Compute Queues IP > Dump\n"); > + adev->gfx.ip_dump_compute_queues = NULL; > + } else { > + adev->gfx.ip_dump_compute_queues = ptr; > + } > +} > + > +static void gfx_v12_1_ip_print(struct amdgpu_ip_block *ip_block, > + struct drm_printer *p) > +{ > + struct amdgpu_device *adev = ip_block->adev; > + uint32_t i, j, k; > + uint32_t xcc_id, xcc_offset, inst_offset; > + uint32_t num_xcc, reg, num_inst; > + uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_1); > + > + if (!adev->gfx.ip_dump_core) > + return; > + > + num_xcc = NUM_XCC(adev->gfx.xcc_mask); > + drm_printf(p, "Number of Instances:%d\n", num_xcc); > + for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { > + xcc_offset = xcc_id * reg_count; > + drm_printf(p, "\nInstance id:%d\n", xcc_id); > + for (i = 0; i < reg_count; i++) > + drm_printf(p, "%-50s \t 0x%08x\n", > + gc_reg_list_12_1[i].reg_name, > + adev->gfx.ip_dump_core[xcc_offset + i]); > + } > + > + /* print compute queue registers for all instances */ > + if (!adev->gfx.ip_dump_compute_queues) > + return; > + > + reg_count = ARRAY_SIZE(gc_cp_reg_list_12_1); > + drm_printf(p, "\nnum_xcc: %d num_mec: %d num_pipe: %d num_queue: > %d\n", > + num_xcc, > + adev->gfx.mec.num_mec, > + adev->gfx.mec.num_pipe_per_mec, > + adev->gfx.mec.num_queue_per_pipe); > + > + for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { > + xcc_offset = xcc_id * reg_count * num_inst; > + inst_offset = 0; > + for (i = 0; i < adev->gfx.mec.num_mec; i++) { > + for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { > + for (k = 0; k < > adev->gfx.mec.num_queue_per_pipe; k++) { > + drm_printf(p, > + "\nxcc:%d mec:%d, pipe:%d, > queue:%d\n", > + xcc_id, i, j, k); > + for (reg = 0; reg < reg_count; reg++) > { > + drm_printf(p, > + "%-50s \t > 0x%08x\n", > + > gc_cp_reg_list_12_1[reg].reg_name, > + > adev->gfx.ip_dump_compute_queues > + [xcc_offset + > inst_offset + > + reg]); > + } > + inst_offset += reg_count; > + } > + } > + } > + } > +} > + > +static void gfx_v12_1_ip_dump(struct amdgpu_ip_block *ip_block) > +{ > + struct amdgpu_device *adev = ip_block->adev; > + uint32_t i, j, k; > + uint32_t num_xcc, reg, num_inst; > + uint32_t xcc_id, xcc_offset, inst_offset; > + uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_1); > + > + if (!adev->gfx.ip_dump_core) > + return; > + > + num_xcc = NUM_XCC(adev->gfx.xcc_mask); > + > + amdgpu_gfx_off_ctrl(adev, false); > + for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { > + xcc_offset = xcc_id * reg_count; > + for (i = 0; i < reg_count; i++) > + adev->gfx.ip_dump_core[xcc_offset + i] = > + > RREG32(SOC15_REG_ENTRY_OFFSET_INST(gc_reg_list_12_1[i], > + > GET_INST(GC, xcc_id))); > + } > + amdgpu_gfx_off_ctrl(adev, true); > + > + /* dump compute queue registers for all instances */ > + if (!adev->gfx.ip_dump_compute_queues) > + return; > + > + num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * > + adev->gfx.mec.num_queue_per_pipe; > + reg_count = ARRAY_SIZE(gc_cp_reg_list_12_1); > + amdgpu_gfx_off_ctrl(adev, false); > + mutex_lock(&adev->srbm_mutex); > + for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { > + xcc_offset = xcc_id * reg_count * num_inst; > + inst_offset = 0; > + for (i = 0; i < adev->gfx.mec.num_mec; i++) { > + for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { > + for (k = 0; k < > adev->gfx.mec.num_queue_per_pipe; k++) { > + /* ME0 is for GFX so start from 1 for > CP */ > + soc_v1_0_grbm_select(adev, 1 + i, j, > k, 0, > + GET_INST(GC, > xcc_id)); > + > + for (reg = 0; reg < reg_count; reg++) > { > + > adev->gfx.ip_dump_compute_queues > + [xcc_offset + > + inst_offset + reg] = > + > RREG32(SOC15_REG_ENTRY_OFFSET_INST( > + > gc_cp_reg_list_12_1[reg], > + > GET_INST(GC, xcc_id))); > + } > + inst_offset += reg_count; > + } > + } > + } > + } > + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, 0); > + mutex_unlock(&adev->srbm_mutex); > + amdgpu_gfx_off_ctrl(adev, true); > +} > + > static int gfx_v12_1_sw_init(struct amdgpu_ip_block *ip_block) > { > uint16_t major_ver, minor_ver; > @@ -1282,6 +1550,8 @@ static int gfx_v12_1_sw_init(struct amdgpu_ip_block > *ip_block) > if (r) > return r; > > + gfx_v12_1_alloc_ip_dump(adev); > + > r = amdgpu_gfx_sysfs_init(adev); > if (r) > return r; > @@ -1325,6 +1595,9 @@ static int gfx_v12_1_sw_fini(struct amdgpu_ip_block > *ip_block) > gfx_v12_1_free_microcode(adev); > amdgpu_gfx_sysfs_fini(adev); > > + kfree(adev->gfx.ip_dump_core); > + kfree(adev->gfx.ip_dump_compute_queues); > + > return 0; > } > > @@ -3905,6 +4178,8 @@ static const struct amd_ip_funcs gfx_v12_1_ip_funcs = { > .set_clockgating_state = gfx_v12_1_set_clockgating_state, > .set_powergating_state = gfx_v12_1_set_powergating_state, > .get_clockgating_state = gfx_v12_1_get_clockgating_state, > + .dump_ip_state = gfx_v12_1_ip_dump, > + .print_ip_state = gfx_v12_1_ip_print, > }; > > static const struct amdgpu_ring_funcs gfx_v12_1_ring_funcs_compute = { > -- > 2.54.0 >
