Fix up various things in the GFX6 code to prepare it
to work with IP block soft reset. The main challenge
was figuring out how to properly initialize the
compute queues so that they work well after a reset,
as well as realizing that on GFX6 the compute queues
also have a PFP (as opposed to GFX7+ where PFP is
a graphics only thing). There are also other minor
fixes.
Implement GFX6 IP block soft reset: just reset everything
in the GFX IP block (instead of taking a guess at which
parts need to be reset) to make it consistent, and
also handle clock and power gating to make sure not to
degrade GPU functionality after a GFX IP block soft reset.
This improves current user experience on all GFX6 chips:
On GFX6 dGPUs, the current GPU recovery method
always clears the contents of VRAM, which means that
a buggy (hanging) app can crash the whole graphical
session, which is less than ideal.
Using GFX IP block soft reset means that we can now
move on from GFX hangs on dGPUs without crashing the
whole system.
Tested on the following chips:
Tahiti (FirePro W9000, Radeon HD 7870 XT)
Cape Verde (Radeon R7 450)
Pitcairn (Radeon R9 270X)
Oland (Radeon 430)
Timur Kristóf (11):
drm/amdgpu/gfx6: Improve emit_cntxcntl()
drm/amdgpu/gfx6: Fixup emitting SWITCH_BUFFER packets
drm/amdgpu/gfx6: Use PFP on the compute queues too
drm/amdgpu/gfx6: Initialize compute rings before CP start
drm/amdgpu/gfx6: Clean up rings during reset
drm/amdgpu/gfx6: Execute CLEAR_STATE when initializing compute rings
drm/amdgpu/gfx6: Properly enable/disable priv_req and priv_inst
interrupts
drm/amdgpu/gfx6: Adjust how harvested TCCs are set up
drm/amdgpu/gfx6: Use COND_EXEC
drm/amdgpu/gfx6: Add IP block soft reset implementation
drm/amdgpu/gfx6: Enable IP block soft reset as a GPU recovery method
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 403 +++++++++++++-----
.../include/asic_reg/gca/gfx_6_0_sh_mask.h | 32 +-
2 files changed, 316 insertions(+), 119 deletions(-)
--
2.55.0
