AMD General Best Regards, Thomas -----Original Message----- From: amd-gfx <[email protected]> On Behalf Of Zhou1, Tao Sent: Wednesday, July 15, 2026 5:35 PM To: Zhang, Hawking <[email protected]>; [email protected] Subject: RE: [PATCH 4/5] drm/amd/ras: add real ras deferred error count
AMD General > -----Original Message----- > From: Zhang, Hawking <[email protected]> > Sent: Wednesday, July 15, 2026 5:29 PM > To: Zhou1, Tao <[email protected]>; [email protected] > Cc: Zhou1, Tao <[email protected]> > Subject: RE: [PATCH 4/5] drm/amd/ras: add real ras deferred error > count > > AMD General > > Can we just use ACA_REG__MISC0__ERRCNT instead? Was trying to > understand the use of real_de_count > > Regards, > Hawking >[Tao] as you can see in aca_parse_bank_default: > if (aca_check_bank_is_de(ras_core, status)) { > ecc->de_count = 0; >... >for non-umc blocks, the ecc->de_count is 0 even aca_check_bank_is_de is true, >so I introduce real_de_count to represent the status of aca_check_bank_is_de. [Thomas] Can we add disable ce log check to here? If ce log is disabled then set ecc->de_count = 1, so that not need to introduce a new variable? BRs, Tao > > -----Original Message----- > From: amd-gfx <[email protected]> On Behalf Of Tao > Zhou > Sent: Wednesday, July 15, 2026 3:48 PM > To: [email protected] > Cc: Zhou1, Tao <[email protected]> > Subject: [PATCH 4/5] drm/amd/ras: add real ras deferred error count > > It only depends on the status of ras bank register, and can be used in > common aca layer. > > Signed-off-by: Tao Zhou <[email protected]> > --- > drivers/gpu/drm/amd/ras/rascore/ras_aca.h | 2 ++ > drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c | 18 > +++++++++++------- > 2 files changed, 13 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_aca.h > b/drivers/gpu/drm/amd/ras/rascore/ras_aca.h > index f61b02a5f0fc..0bde803f7472 100644 > --- a/drivers/gpu/drm/amd/ras/rascore/ras_aca.h > +++ b/drivers/gpu/drm/amd/ras/rascore/ras_aca.h > @@ -83,6 +83,8 @@ struct aca_bank_ecc { > u32 ce_count; > u32 ue_count; > u32 de_count; > + /* only depends on bank reg status */ > + u32 real_de_count; > }; > > struct aca_ecc_count { > diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c > b/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c > index 840610538c1f..41df331587a0 100644 > --- a/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c > +++ b/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c > @@ -207,6 +207,13 @@ static bool aca_check_umc_ce(struct > ras_core_context *ras_core, uint64_t mc_umc_ > !(aca_check_umc_ue(ras_core, mc_umc_status))))); > } > > +static bool aca_check_bank_is_de(struct ras_core_context *ras_core, > + uint64_t status) { > + return (ACA_REG_STATUS_POISON(status) || > + ACA_REG_STATUS_DEFERRED(status)); } > + > static int aca_parse_umc_bank(struct ras_core_context *ras_core, > struct aca_block *ras_blk, void *data, void > *buf) { @@ -230,6 +237,9 @@ static int aca_parse_umc_bank(struct > ras_core_context *ras_core, > ext_error_code = ACA_REG_STATUS_ERRORCODEEXT(status0); > misc0_errcnt = ACA_REG_MISC0_ERRCNT(bank- > >regs[ACA_REG_IDX__MISC0]); > > + if (aca_check_bank_is_de(ras_core, status0)) > + ecc->real_de_count = misc0_errcnt ? misc0_errcnt : 1; > + > if (aca_check_umc_de(ras_core, status0)) > ecc->de_count = misc0_errcnt ? misc0_errcnt : 1; > else if (aca_check_umc_ue(ras_core, status0)) @@ -240,13 > +250,6 @@ static int aca_parse_umc_bank(struct ras_core_context *ras_core, > return 0; > } > > -static bool aca_check_bank_is_de(struct ras_core_context *ras_core, > - uint64_t status) > -{ > - return (ACA_REG_STATUS_POISON(status) || > - ACA_REG_STATUS_DEFERRED(status)); > -} > - > static int aca_parse_bank_default(struct ras_core_context *ras_core, > struct aca_block *ras_blk, > void *data, void *buf) @@ -266,6 > +269,7 @@ static int aca_parse_bank_default(struct ras_core_context > *ras_core, > > if (aca_check_bank_is_de(ras_core, status)) { > ecc->de_count = 0; > + ecc->real_de_count = 1; > } else { > if (bank->ecc_type == RAS_ERR_TYPE__UE) > ecc->ue_count = 1; > -- > 2.34.1 >
