On Tue, Aug 4, 2026 at 3:28 AM Travis B <[email protected]> wrote: > > From: Travis K. Bangs <[email protected]> > > The VBIOS for Cyan Skillfish devices (DCN201) indicates there is > DisplayPort ref clock spread spectrum downspread, so the audio clock > is corrected for it. > > However, the clock source in this hardware does not seem to actually be > running with a clock downspread, so DisplayPort audio desyncs with video > after several minutes. > > Ignore dprefclk SS downspread on CYAN_SKILLFISH2 asic. > > Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/5429 > Signed-off-by: Travis K. Bangs <[email protected]>
Applied. Thanks! Alex > > --- > Submitting this patch as requested by Alex Deucher. > > The system with this problem is the ASRock BC-250, which to my knowledge > is the only GPU which uses DCN 201, so this should not affect anything > else. I have tested this patch on my system. > > Some relevant register reads: > dprefclk is set based on the value of register CLK4_CLK2_CURRENT_CNT > which reads as 6000. > > Without this patch DCCG_AUDIO_DTO1_MODULE gets set to 598874. > With this patch DCCG_AUDIO_DTO1_MODULE gets set to 600000 and audio > stays in sync. > > I am in contact with about a dozen other BC-250 users who have also used > this patch and reported that it solved their desync. > > There might be a deeper underlying bug here but I think it takes AMD > insider knowledge to fully understand what is happening. I am glad to > provide further info or do further testing if needed. > > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > index 1820547b1dde..941c1a312824 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > @@ -2189,6 +2189,11 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) > init_data.flags.unify_link_enc_assignment = true; > init_data.flags.usb4_bw_alloc_support = true; > } > + > + /* DCN201 audio desyncs using DP SS */ > + if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) > + init_data.flags.ignore_dpref_ss = true; > + > retrieve_dmi_info(&adev->dm); > if (adev->dm.edp0_on_dp1_quirk) > init_data.flags.support_edp0_on_dp1 = true;
